Ð
þídl8^@(,^)tronsmart,orion-r68-metarockchip,rk3368+7Rockchip Orion R68aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000…/serial@ff1c0000/spi@ff110000’/spi@ff120000—/spi@ff130000cpus+cpu-mapcluster0core0œcore1œcore2œcore3œcluster1core0œcore1œcore2œcore3œ cpu@0 cpuarm,cortex-a53¬°psci¾Ícpu@1 cpuarm,cortex-a53¬°psci¾Ícpu@2 cpuarm,cortex-a53¬°psci¾Ícpu@3 cpuarm,cortex-a53¬°psci¾Í cpu@100 cpuarm,cortex-a53¬°psci¾Ícpu@101 cpuarm,cortex-a53¬°psci¾Ícpu@102 cpuarm,cortex-a53¬°psci¾Ícpu@103 cpuarm,cortex-a53¬°psci¾Íambasimple-bus+Õdma-controller@ff250000arm,pl330arm,primecell¬ÿ%@Üçò
à apb_pclkdma-controller@ff600000arm,pl330arm,primecell¬ÿ`@Üçò
 apb_pclkÍ9arm-pmuarm,armv8-pmuv3`Üpqrstuvw psci
arm,psci-0.2·smctimerarm,armv8-timer0Ü
ÿÿÿ
ÿoscillatorfixed-clock3n6Cxin24mVdwmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ@cúð€
È
D
r
vbiuciuciu-driveciu-sampleqÜ |
€ƒresetokay–3úð€ ±ÈÃdefaultÑ
Ûçdwmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ
@cðÑ€
É
E
s
wbiuciuciu-driveciu-sampleqÜ!|
ƒreset disableddwmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ@cðÑ€
Ë
G
u
ybiuciuciu-driveciu-sampleqÜ#|
ƒƒresetokay–ô /ÃdefaultÑsaradc@ff100000rockchip,saradc¬ÿÜ$=
I
[saradcapb_pclk|
Wƒsaradc-apbokayOspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ
A
Rspiclkapb_pclkÜ,ÃdefaultÑ+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ
B
Sspiclkapb_pclkÜ-ÃdefaultÑ+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ
C
Tspiclkapb_pclkÜ)ÃdefaultÑ !+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿÜ>+i2c
NÃdefaultÑ" disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿÜ?+i2c
OÃdefaultÑ# disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿÜ@+i2c
PÃdefaultÑ$ disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿÜA+i2c
QÃdefaultÑ% disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿ3n6
M
Ubaudclkapb_pclkÜ7[e disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿ3n6
N
Vbaudclkapb_pclkÜ8[e disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿ3n6
P
Xbaudclkapb_pclkÜ:[e disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿ3n6
Q
Ybaudclkapb_pclkÜ;[eokayÃdefaultÑ&thermal-zonescpurdˆˆ–'tripscpu_alert0¦$ø²Ð§passiveÍ(cpu_alert1¦8€²Ð§passiveÍ)cpu_crit¦s²Ð §criticalcooling-mapsmap0½(0Âÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1½)0Âÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpurdˆˆ–'tripsgpu_alert0¦8€²Ð§passiveÍ*gpu_crit¦Á8²Ð §criticalcooling-mapsmap0½*0Âÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3368-tsadc¬ÿ(Ü%
H
Ztsadcapb_pclk|
Ÿ
ƒtsadc-apbÃinitdefaultsleepÑ+Ñ,Û+åûs disabledÍ'ethernet@ff290000rockchip,rk3368-gmac¬ÿ)Ümacirq"-8
f
g
c
€
Å
]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macok/
?.Vinputc/nrgmiiÃdefaultÑ0w1‡'B@²0»usb@ff500000
generic-ehci¬ÿPÜ
Âusbhostokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2¬ÿXÜ
ÁotgÄotgÌÞ퀀@@ okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿe
Li2cÜ<�ÃdefaultÑ2+okaysyr827@40silergy,syr827¬@üvdd_cpu(,D
ß4\ã`t@‰¯3hym8563@51haoyu,hym8563¬QV3€Cxin32ki2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿfÜ=+i2c
MÃdefaultÑ4 disabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿhºÃdefaultÑ5
_pwm disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿhºÃdefaultÑ6
_pwm disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh º
_pwm disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh0ºÃdefaultÑ7
_pwm disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿi
O
Wbaudclkapb_pclkÜ9ÃdefaultÑ8[eokaymbox@ff6b0000rockchip,rk3368-mailbox¬ÿk0Ü’“”•
E
pclk_mailboxÅ disabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfd¬ÿs€Í<�io-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-modeÑØRBÃäRBÃòRBà RBÃclock-controller@ff760000rockchip,rk3368-cru¬ÿv"-VÍ
syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfd¬ÿwÍ-io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt¬ÿ€
pÜOokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer¬ÿ ÜBspdif@ff880000rockchip,rk3368-spdif¬ÿˆÜ6
S
Ð
mclkhclk9 txÃdefaultÑ: disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s¬ÿ‰Ü(i2s_clki2s_hclk
T
Î99 txrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s¬ÿ‰€Ü5i2s_clki2s_hclk
R
Ï99 txrxÃdefaultÑ; disablediommu@ff900800rockchip,iommu¬ÿÜiep_mmu
Ê
Ôaclkiface* disablediommu@ff914000rockchip,iommu ¬ÿ‘@ÿ‘PÜisp_mmu
Í
Õaclkiface*7 disablediommu@ff930300rockchip,iommu¬ÿ“Üvop_mmu
Æ
Ñaclkiface* disablediommu@ff9a0440rockchip,iommu ¬ÿš@@ÿš€@Ü hevc_mmu
Ð
Üaclkiface* disablediommu@ff9a0800rockchip,iommu¬ÿšÜ
vepu_mmuvdpu_mmu
Ð
Üaclkiface* disabledefuse@ffb00000rockchip,rk3368-efuse¬ÿ° +
qpclk_efusecpu-leakage@17¬temp-adjust@1f¬interrupt-controller@ffb71000arm,gic-400Rg@¬ÿ·ÿ· ÿ·@ ÿ·` Ü ÿÍpinctrlrockchip,rk3368-pinctrl"-x<�+Õgpio0@ff750000rockchip,gpio-bank¬ÿu
@ÜQ…•RgÍFgpio1@ff780000rockchip,gpio-bank¬ÿx
AÜR…•Rggpio2@ff790000rockchip,gpio-bank¬ÿy
BÜS…•RgÍDgpio3@ff7a0000rockchip,gpio-bank¬ÿz
CÜT…•RgÍ1pcfg-pull-up¡Í?pcfg-pull-down®ÍBpcfg-pull-none½Í@pcfg-pull-none-12ma½ÊÍAemmcemmc-clkÙ=Íemmc-cmdÙ>Íemmc-pwrÙ?emmc-bus1Ù?emmc-bus4@Ù????emmc-bus8€Ù>>>>>>>>Íemmc-resetÙ@ÍCgmacrgmii-pinsðÙ@@@A A
AAA
A@@@@@@Í0rmii-pins Ù@@@A A
A@@@@i2c0i2c0-xfer Ù@@Í2i2c1i2c1-xfer Ù@@Í4i2c2i2c2-xfer Ù @@Í"i2c3i2c3-xfer Ù@@Í#i2c4i2c4-xfer Ù@@Í$i2c5i2c5-xfer Ù@@Í%i2si2s-8ch-busÙ@
@@@@@@@@Í;pwm0pwm0-pinÙ@Í5pwm1pwm1-pinÙ@Í6pwm3pwm3-pinÙ@Í7sdio0sdio0-bus1Ù?sdio0-bus4@Ù????sdio0-cmdÙ?sdio0-clkÙ@sdio0-cdÙ?sdio0-wpÙ?sdio0-pwrÙ?sdio0-bkpwrÙ?sdio0-intÙ?sdmmcsdmmc-clkÙ =Ísdmmc-cmdÙ
>Ísdmmc-cdÙ>Í
sdmmc-bus1Ù>sdmmc-bus4@Ù>>>>Íspdifspdif-txÙ@Í:spi0spi0-clkÙ?Íspi0-cs0Ù?Íspi0-cs1Ù?spi0-txÙ?Íspi0-rxÙ?Íspi1spi1-clkÙ?Íspi1-cs0Ù?Íspi1-cs1Ù?spi1-rxÙ?Íspi1-txÙ?Íspi2spi2-clkÙ?Íspi2-cs0Ù
?Í!spi2-rxÙ
?Í spi2-txÙ?Ítsadcotp-gpioÙ@Í+otp-outÙ@Í,uart0uart0-xfer Ù?@uart0-ctsÙ@uart0-rtsÙ@uart1uart1-xfer Ù?@uart1-ctsÙ@uart1-rtsÙ@uart2uart2-xfer Ù?@Í8uart3uart3-xfer Ù?@uart3-ctsÙ@uart3-rtsÙ@uart4uart4-xfer Ù?@Í&uart4-ctsÙ@uart4-rtsÙ@pcfg-pull-none-drv-8ma½ÊÍ=pcfg-pull-up-drv-8ma¡ÊÍ>keyspwr-keyÙBÍEledsstby-pwrenÙ@ÍHled-ctlÙ@ÍGusbhost-vbus-drvÙ@ÍIchosençserial2:115200n8memory memory¬€emmc-pwrseqmmc-pwrseq-emmcÑCÃdefaultóDÍexternal-gmac-clockfixed-clockV3sY@ Cext_gmacÍ.gpio-keys
gpio-keysÃdefaultÑEpowerÿùF
GPIO Powertgpio-leds
gpio-ledsredù1
orion:red:ledÃdefaultÑGonblueùF
orion:blue:ledÃdefaultÑHoffvcc18-regulatorregulator-fixedvcc_18Dw@\w@‰¯3Ívcc-host-regulatorregulator-fixed‚FÃdefaultÑI vcc_host‰¯3vcc-io-regulatorregulator-fixedvcc_ioD2Z \2Z ‰¯3ÍJvcc-lan-regulatorregulator-fixedvcc_lanD2Z \2Z ‰¯JÍ/vcc-sd-regulatorregulator-fixedvcc_sd‚1Dw@\2Z ¯JÍvcc-sys-regulatorregulator-fixedvcc_sysDLK@\LK@‰Í3vcc-io-sd-regulatorregulator-fixed vccio_sdDw@\2Z ‰¯JÍvccio-wl-regulatorregulator-fixed vccio_wlD2Z \2Z ‰¯Jvdd-10-regulatorregulator-fixedvdd_10DB@\B@‰¯3 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellsphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-sd-highspeedcard-detect-delaypinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqmmc-hs200-1_2vmmc-hs200-1_8vnon-removable#io-channel-cellsvref-supplyreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codedefault-state