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+ext_clock°# interrupt-parent#address-cells#size-cellsmodelcompatiblerangesstdout-pathallwinner,pipelineclocksstatusvcc-hdmi-supplydevice_typeregenable-methodnext-level-cachephandlecache-levelallwinner,pipelines#clock-cellsclock-frequencyclock-output-namesinterruptsinterrupt-affinitysimple-audio-card,namesimple-audio-card,formatsimple-audio-card,frame-mastersimple-audio-card,bitclock-mastersimple-audio-card,mclk-fssimple-audio-card,aux-devssimple-audio-card,routingsound-dai#sound-dai-cellsallwinner,erratum-unknown1allwinner,sramclock-namesresets#reset-cellsremote-endpointdma-channelsdma-requests#dma-cellsreset-namesmax-frequencypinctrl-namespinctrl-0vmmc-supplycd-gpiosdisable-wpbus-widthvqmmc-supplymmc-pwrseqnon-removableinterrupt-namesphysphy-namesextcondr_modereg-names#phy-cellsusb0_id_det-gpiosusb0_vbus-supplyusb1_vbus-supplygpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinsfunctiondrive-strengthbias-pull-updmasdma-namesreg-shiftreg-io-widthuart-has-rtsctsmax-speedvbat-supplyvddio-supplydevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosnum-csspi-max-frequencym25p,fast-readsysconphy-modephy-handlephy-supply#pwm-cellshvcc-supplyx-powers,drive-vbus-en#io-channel-cellsx-powers,dcdc-freqregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onethernet0serial0serial1serial2serial3serial4labelregulator-boot-onenable-active-highgpioreset-gpios