Ð þí sHÄ(¯|€RTSM_VE_AEMv8A arm,rtsm_ve,aemv8aarm,vexpress"1smb@8000000 simple-bus"1x= D U?´h            !!""##$$%%&&''(())**motherboardvrs1arm,vexpress,v2m-p1simple-bus"1D=flash@0,00000000arm,vexpress-flashcfi-flash‰ethernet@2,02000000smsc,lan91c111 ‰˜clk24mhz fixed-clock£°n6 Àv2m:clk24mhzÓrefclk1mhz fixed-clock£°B@Àv2m:refclk1mhzÓrefclk32khz fixed-clock£°€Àv2m:refclk32khzÓiofpga@3,00000000 simple-bus"1= sysreg@10000arm,vexpress-sysreg‰ÛëÓsysctl@20000arm,sp810arm,primecell‰ ÷þrefclktimclkapb_pclk£0Àtimerclken0timerclken1timerclken2timerclken3  Óaaci@40000arm,pl041arm,primecell‰˜ ÷ þapb_pclkmmci@50000arm,pl180arm,primecell‰˜  1 :C·Q÷þmclkapb_pclkkmi@60000arm,pl050arm,primecell‰˜ ÷þKMIREFCLKapb_pclkkmi@70000arm,pl050arm,primecell‰˜ ÷þKMIREFCLKapb_pclkuart@90000arm,pl011arm,primecell‰ ˜÷þuartclkapb_pclkuart@a0000arm,pl011arm,primecell‰ ˜÷þuartclkapb_pclkuart@b0000arm,pl011arm,primecell‰ ˜÷þuartclkapb_pclkuart@c0000arm,pl011arm,primecell‰ ˜÷þuartclkapb_pclkwdt@f0000arm,sp805arm,primecell‰˜÷þwdogclkapb_pclktimer@110000arm,sp804arm,primecell‰˜÷þtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecell‰˜÷þtimclken1timclken2apb_pclkvirtio-block@130000 virtio,mmio‰˜*rtc@170000arm,pl031arm,primecell‰˜÷ þapb_pclkclcd@1f0000arm,pl111arm,primecell‰ ]combined˜÷þclcdclkapb_pclkm portendpoint{  ‹Ó v2m-3v3regulator-fixed¥3V3´2Z Ì2Z äÓmccarm,vexpress,config-busøoscclk1arm,vexpress-osc,jepÈî࣠Àv2m:oscclk1Óresetarm,vexpress-resetmuxfpgaarm,vexpress-muxfpgashutdownarm,vexpress-shutdownrebootarm,vexpress-reboot dvimodearm,vexpress-dvimode chosenaliases67/smb@8000000/motherboard/iofpga@3,00000000/uart@900006?/smb@8000000/motherboard/iofpga@3,00000000/uart@a00006G/smb@8000000/motherboard/iofpga@3,00000000/uart@b00006O/smb@8000000/motherboard/iofpga@3,00000000/uart@c0000cpus"1cpu@0Wcpu arm,armv8‰ cspin-tableq€ÿø‚ cpu@1Wcpu arm,armv8‰ cspin-tableq€ÿø‚ cpu@2Wcpu arm,armv8‰ cspin-tableq€ÿø‚ cpu@3Wcpu arm,armv8‰ cspin-tableq€ÿø‚ l2-cache0cacheÓ memory@80000000Wmemory ‰€€€€reserved-memory"1=vram@18000000shared-dma-pool‰€“Ó interrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gicD"š@‰,, ,@ ,`  ˜ Ótimerarm,armv8-timer0˜   °õápmuarm,armv8-pmuv30˜<�=>?panelarm,rtsm-displayportendpoint{ Ó  modelcompatibleinterrupt-parent#address-cells#size-cellsranges#interrupt-cellsinterrupt-map-maskinterrupt-maparm,v2m-memory-mapregbank-widthinterrupts#clock-cellsclock-frequencyclock-output-namesphandlegpio-controller#gpio-cellsclocksclock-namesassigned-clocksassigned-clock-parentscd-gpioswp-gpiosmax-frequencyvmmc-supplyinterrupt-namesmemory-regionremote-endpointarm,pl11x,tft-r0g0b0-padsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangeserial0serial1serial2serial3device_typeenable-methodcpu-release-addrnext-level-cacheno-mapinterrupt-controller