Ð þíb#8[¸(k[€.rockchip,px5-evbrockchip,px5rockchip,rk3368 +7Rockchip PX5 EVBaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000…/serial@ff1c0000/spi@ff110000’/spi@ff120000—/spi@ff130000cpus+cpu-mapcluster0core0œcore1œcore2œcore3œcluster1core0œcore1œcore2œcore3œ cpu@0 cpuarm,cortex-a53¬°psci¾Ícpu@1 cpuarm,cortex-a53¬°psci¾Ícpu@2 cpuarm,cortex-a53¬°psci¾Ícpu@3 cpuarm,cortex-a53¬°psci¾Í cpu@100 cpuarm,cortex-a53¬°psci¾Ícpu@101 cpuarm,cortex-a53¬°psci¾Ícpu@102 cpuarm,cortex-a53¬°psci¾Ícpu@103 cpuarm,cortex-a53¬°psci¾Íamba simple-bus+Õdma-controller@ff250000arm,pl330arm,primecell¬ÿ%@Üçò à apb_pclkdma-controller@ff600000arm,pl330arm,primecell¬ÿ`@Üçò  apb_pclkÍ9arm-pmuarm,armv8-pmuv3`Üpqrstuvw   psci arm,psci-0.2·smctimerarm,armv8-timer0Ü ÿÿ ÿ ÿoscillator fixed-clock3n6Cxin24mVdwmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ @cðÑ€  È D r vbiuciuciu-driveciu-sampleq Ü | €ƒresetokay– ²ÃÈÕÝåòÿdefault Z5Adwmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ @cðÑ€  É E s wbiuciuciu-driveciu-sampleq Ü!| ƒreset disableddwmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ@cðÑ€  Ë G u ybiuciuciu-driveciu-sampleq Ü#| ƒƒresetokay– 3ðÑ€NÝ]cÿdefault  5Asaradc@ff100000rockchip,saradc¬ÿ Ü$q I [saradcapb_pclk| W ƒsaradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ A Rspiclkapb_pclk Ü,ÿdefault + disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ B Sspiclkapb_pclk Ü-ÿdefault + disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ C Tspiclkapb_pclk Ü)ÿdefault  !+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ Ü>+i2c Nÿdefault "okaytouchscreen@40silead,gsl1680¬@ #Ü ƒ# ¢µi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ Ü?+i2c Oÿdefault $ disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ Ü@+i2c Pÿdefault % disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ ÜA+i2c Qÿdefault & disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿ3n6 M Ubaudclkapb_pclk Ü7ÈÒ disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿ3n6 N Vbaudclkapb_pclk Ü8ÈÒ disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿ3n6 P Xbaudclkapb_pclk Ü:ÈÒ disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿ3n6 Q Ybaudclkapb_pclk Ü;Èҏokaythermal-zonescpußdõˆ'tripscpu_alert0$øЧpassiveÍ(cpu_alert18€Ð§passiveÍ)cpu_critsÐ §criticalcooling-mapsmap0*(0/ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1*)0/ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpußdõˆ'tripsgpu_alert08€Ð§passiveÍ*gpu_critÁ8Ð §criticalcooling-mapsmap0**0/ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3368-tsadc¬ÿ( Ü% H Ztsadcapb_pclk| Ÿ ƒtsadc-apbÿinitdefaultsleep +>,H+Rhsokay–Í'ethernet@ff290000rockchip,rk3368-gmac¬ÿ) ܱmacirqÁ-8  f g c € Å ]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac disabledusb@ff500000 generic-ehci¬ÿP Ü Âusbhostokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2¬ÿX Ü ÁotgÎotgÖè÷€€@@ okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿe Li2c Ü<�ÿdefault .+okaypmic@1brockchip,rk808¬ /Üÿdefault 01'232?2K2W2c2o{2‡2”2¡Cxin32krk808-clkout2VregulatorsDCDC_REG1®ÂÔ ®`ìã`vdd_cpuDCDC_REG2®ÂÔ ®`ìã`vdd_logDCDC_REG3®Âvcc_ddrDCDC_REG4®ÂÔ2Z ì2Z vcc_ioÍLDO_REG1®ÂÔw@ìw@ vcc18_flashÍLDO_REG2®ÂÔ2Z ì2Z vcca_33LDO_REG3®ÂÔB@ìB@vdd_10LDO_REG4Ô2Z ì2Z avdd_33LDO_REG5®ÂÔw@ì2Z  vccio_sdÍLDO_REG6®ÂÔB@ìB@ vdd10_lcdLDO_REG7®ÂÔw@ìw@vcc_18LDO_REG8®ÂÔw@ìw@ vcc18_lcdSWITCH_REG1vcc_sdÍSWITCH_REG2®Â vcc33_lcdi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿf Ü=+i2c Mÿdefault 3okayaccelerometer@18 bosch,bma250¬ 4Üpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿhÿdefault 5 _pwm disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿhÿdefault 6 _pwm disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh  _pwm disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh0ÿdefault 7 _pwm disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿi O Wbaudclkapb_pclk Ü9ÿdefault 8ÈÒ disabledmbox@ff6b0000rockchip,rk3368-mailbox¬ÿk0Ü’“”• E pclk_mailbox disabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfd¬ÿs€Í<�io-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-mode*1RBÃ=RBÃKRBà [RBÃclock-controller@ff760000rockchip,rk3368-cru¬ÿvÁ-VgÍ syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfd¬ÿwÍ-io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt¬ÿ€ p ÜOokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer¬ÿ  ÜBspdif@ff880000rockchip,rk3368-spdif¬ÿˆ Ü6 S Ð mclkhclkt9ytxÿdefault : disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s¬ÿ‰ Ü(i2s_clki2s_hclk T Ît99ytxrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s¬ÿ‰€ Ü5i2s_clki2s_hclk R Ït99ytxrxÿdefault ; disablediommu@ff900800rockchip,iommu¬ÿ ܱiep_mmu Ê Ô aclkifaceƒ disablediommu@ff914000rockchip,iommu ¬ÿ‘@ÿ‘P ܱisp_mmu Í Õ aclkifaceƒ disablediommu@ff930300rockchip,iommu¬ÿ“ ܱvop_mmu Æ Ñ aclkifaceƒ disablediommu@ff9a0440rockchip,iommu ¬ÿš@@ÿš€@ Ü  ±hevc_mmu Ð Ü aclkifaceƒ disablediommu@ff9a0800rockchip,iommu¬ÿšÜ  ±vepu_mmuvdpu_mmu Ð Ü aclkifaceƒ disabledefuse@ffb00000rockchip,rk3368-efuse¬ÿ° + q pclk_efusecpu-leakage@17¬temp-adjust@1f¬interrupt-controller@ffb71000 arm,gic-400«À@¬ÿ·ÿ· ÿ·@ ÿ·`  Ü ÿÍpinctrlrockchip,rk3368-pinctrlÁ-Ñ<�+Õgpio0@ff750000rockchip,gpio-bank¬ÿu @ ÜQÞî«ÀÍ/gpio1@ff780000rockchip,gpio-bank¬ÿx A ÜRÞî«Àgpio2@ff790000rockchip,gpio-bank¬ÿy B ÜSÞî«ÀÍ4gpio3@ff7a0000rockchip,gpio-bank¬ÿz C ÜTÞî«ÀÍ#pcfg-pull-upúÍ>pcfg-pull-downpcfg-pull-noneÍ=pcfg-pull-none-12ma# Í?emmcemmc-clk2=Íemmc-cmd2>Íemmc-pwr2>emmc-bus12>emmc-bus4@2>>>>emmc-bus8€2>>>>>>>>Ígmacrgmii-pinsð2===? ? ??? ?======rmii-pins 2===? ? ?====i2c0i2c0-xfer 2==Í.i2c1i2c1-xfer 2==Í3i2c2i2c2-xfer 2 ==Í"i2c3i2c3-xfer 2==Í$i2c4i2c4-xfer 2==Í%i2c5i2c5-xfer 2==Í&i2si2s-8ch-bus2 = ========Í;pwm0pwm0-pin2=Í5pwm1pwm1-pin2=Í6pwm3pwm3-pin2=Í7sdio0sdio0-bus12>sdio0-bus4@2>>>>sdio0-cmd2>sdio0-clk2=sdio0-cd2>sdio0-wp2>sdio0-pwr2>sdio0-bkpwr2>sdio0-int2>sdmmcsdmmc-clk2 =Í sdmmc-cmd2 >Í sdmmc-cd2 >Ísdmmc-bus12>sdmmc-bus4@2>>>>Í spdifspdif-tx2=Í:spi0spi0-clk2>Íspi0-cs02>Íspi0-cs12>spi0-tx2>Íspi0-rx2>Íspi1spi1-clk2>Íspi1-cs02>Íspi1-cs12>spi1-rx2>Íspi1-tx2>Íspi2spi2-clk2 >Íspi2-cs02 >Í!spi2-rx2 >Í spi2-tx2 >Ítsadcotp-gpio2=Í+otp-out2=Í,uart0uart0-xfer 2>=uart0-cts2=uart0-rts2=uart1uart1-xfer 2>=uart1-cts2=uart1-rts2=uart2uart2-xfer 2>=Í8uart3uart3-xfer 2>=uart3-cts2=uart3-rts2=uart4uart4-xfer 2>=uart4-cts2=uart4-rts2=keyspwr-key2=Í@pmicpmic-sleep2=Í1pmic-int2>Í0chosen@serial4:115200n8memory@0¬@ memorygpio-keys gpio-keysÿdefault @power ‰/ LGPIO PowerRt]vcc-sys-regulatorregulator-fixedvcc_sysÔLK@ìLK@®ÂÍ2 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellsphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delayno-emmcno-sdiosd-uhs-sdr12sd-uhs-sdr25pinctrl-namespinctrl-0rockchip,default-sample-phasevmmc-supplyvqmmc-supplymmc-hs200-1_8vno-sdnon-removable#io-channel-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingersreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathlabellinux,codewakeup-source