Ð þíh;8aü(?aÄ,rockchip,rk3368-evb-act8846rockchip,rk3368 +&7Rockchip RK3368 EVB with ACT8846 pmicaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000…/serial@ff1c0000/spi@ff110000’/spi@ff120000—/spi@ff130000cpus+cpu-mapcluster0core0œcore1œcore2œcore3œcluster1core0œcore1œcore2œcore3œ cpu@0 cpuarm,cortex-a53¬°psci¾Ícpu@1 cpuarm,cortex-a53¬°psci¾Ícpu@2 cpuarm,cortex-a53¬°psci¾Ícpu@3 cpuarm,cortex-a53¬°psci¾Í cpu@100 cpuarm,cortex-a53¬°psci¾Ícpu@101 cpuarm,cortex-a53¬°psci¾Ícpu@102 cpuarm,cortex-a53¬°psci¾Ícpu@103 cpuarm,cortex-a53¬°psci¾Íamba simple-bus+Õdma-controller@ff250000arm,pl330arm,primecell¬ÿ%@Üçò à apb_pclkdma-controller@ff600000arm,pl330arm,primecell¬ÿ`@Üçò  apb_pclkÍ2arm-pmuarm,armv8-pmuv3`Üpqrstuvw   psci arm,psci-0.2·smctimerarm,armv8-timer0Ü ÿÿ ÿ ÿoscillator fixed-clock3n6Cxin24mVdwmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ @cðÑ€  È D r vbiuciuciu-driveciu-sampleq Ü | €ƒreset disableddwmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ @cðÑ€  É E s wbiuciuciu-driveciu-sampleq Ü!| ƒreset disableddwmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ@cðÑ€  Ë G u ybiuciuciu-driveciu-sampleq Ü#| ƒƒresetokay– ² ½Ëdefault Ù saradc@ff100000rockchip,saradc¬ÿ Ü$ã I [saradcapb_pclk| W ƒsaradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ A Rspiclkapb_pclk Ü,ËdefaultÙ+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ B Sspiclkapb_pclk Ü-ËdefaultÙ+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ C Tspiclkapb_pclk Ü)ËdefaultÙ+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ Ü>+i2c NËdefaultÙ disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ Ü?+i2c OËdefaultÙ disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ Ü@+i2c PËdefaultÙ disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ ÜA+i2c QËdefaultÙ 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Âusbhostokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2¬ÿX Ü Áotgihostqƒ’€€@@ okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿe Li2c Ü<�ËdefaultÙ)+okay3€syr827@40silergy,syr827¬@¡¾vdd_cpuÍ øPå™pý#*syr828@41silergy,syr828¬A¡¾vdd_gpuÍ øPå™pý#*act8846@5aactive-semi,act8846¬Zokay.*9*D*O*Z+f*r,regulatorsREG1¾VCC_DDRÍO€åO€ýREG2¾VCC_IOÍ2Z å2Z ýÍ+REG3¾VDD_LOGÍ ®`åã`ýREG4¾VCC_20Í„€å„€ýÍ,REG5 ¾VCCIO_SDÍw@å2Z ýREG6 ¾VDD10_LCDÍB@åB@ýREG7 ¾VCCA_CODECÍ2Z å2Z ýREG8¾VCCA_TPÍ2Z å2Z ýREG9 ¾VCCIO_PMUÍ2Z å2Z ýREG10¾VDD_10ÍB@åB@ýREG11¾VCC_18Íw@åw@ýREG12 ¾VCC18_LCDÍw@åw@ýi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿf Ü=+i2c MËdefaultÙ- disabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh~ËdefaultÙ. _pwmokayÍ=pwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh~ËdefaultÙ/ _pwm disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh ~ _pwm disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh0~ËdefaultÙ0 _pwm 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!"#$%&'()*+,-./0123456789:;<�=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿÉ€ â;ËdefaultÙ<�ï=B@ô'emmc-pwrseqmmc-pwrseq-emmcÙ>Ëdefault ?Í gpio-keys gpio-keysËdefaultÙ@power  é; GPIO Power!tvcc-host-regulatorregulator-fixed, ';ËdefaultÙA ¾vcc_hostý#*vcc-lan-regulatorregulator-fixed¾vcc_lanÍ2Z å2Z ý#+Í&vcc-sys-regulatorregulator-fixed¾vcc_sysÍLK@åLK@ýÍ* compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellsphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedmmc-pwrseqnon-removablepinctrl-namespinctrl-0#io-channel-cellsreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplyvp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathbrightness-levelsdefault-brightness-levelenable-gpiospwmspwm-delay-usreset-gpioswakeup-sourcelabellinux,codeenable-active-high