Ð þ퇀8((X~ðpine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53‰”£x½psciËÜðûcpu@1}cpuarm,cortex-a53‰”£x½psciËÜðûcpu@2}cpuarm,cortex-a53‰”£x½psciËÜðûcpu@3}cpuarm,cortex-a53‰”£x½psciËÜðû l2-cache0cacheûopp_table0operating-points-v2ûopp-408000000Q–~ð#œ@4opp-600000000#ÃF~ð#œ@opp-8160000000£,B@#œ@opp-1008000000<ÜÈà#œ@opp-1200000000G†Œ±(#œ@opp-1296000000M?dÖ #œ@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell‰ÿ@G† Rapb_pclk^û arm-pmuarm,cortex-a53-pmu0Gdefgi display-subsystemrockchip,display-subsystem| psciarm,psci-1.0arm,psci-0.2Äsmctimerarm,armv8-timer0G   xin24m fixed-clock‚n6Ÿxin24mûAi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G)7Ri2s_clki2s_hclk² ·txrxÁ Òdisabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G*8Ri2s_clki2s_hclk²  ·txrxÁÒokayportûdendpointÙi2säì û@i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G+9Ri2s_clki2s_hclk² ·txrxÁ Òdisabledspdif@ff030000rockchip,rk3328-spdif‰ÿ G.: Rmclkhclk² ·txüdefault ÁÒokayportûeendpointìûfpdm@ff040000 rockchip,pdm‰ÿ=RRpdm_clkpdm_hclk² ·rxüdefaultsleep  Òdisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd‰ÿ+û6io-domains"rockchip,rk3328-io-voltage-domainÒokay,:HVdrgrf-gpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller›+û8pd_hevc@6‰pd_video@5‰pd_vpu@8‰Freboot-modesyscon-reboot-mode¯È¶RBÃÂRBÃÐRBà àRBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G7&ÒRbaudclkapb_pclk²  ·txrxüdefault  ìù Òdisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G8'ÓRbaudclkapb_pclk²  ·txrxüdefault   !ìù Òdisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G9(ÔRbaudclkapb_pclk²  ·txrxüdefault "ìùÒokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G$+7Í Ri2cpclküdefault # Òdisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G%+8Î Ri2cpclküdefault $Òokaypmic@18rockchip,rk805‰ %G‚Ÿxin32krk805-clkout2üdefault &$2'>'J'V'bn'ûcregulatorsDCDC_REG1 zvdd_logic‰ ß4¡ ¹0ÔÎâregulator-state-memô B@DCDC_REG2zvdd_arm‰ ß4¡ ¹0ÔÎâûregulator-state-memô ~ðDCDC_REG3zvcc_ddrÎâregulator-state-memôDCDC_REG4zvcc_io‰2Z ¡2Z Îâûregulator-state-memô 2Z LDO_REG1zvcc_18‰w@¡w@Îâûregulator-state-memô w@LDO_REG2 zvcc18_emmc‰w@¡w@Îâûregulator-state-memô w@LDO_REG3zvdd_10‰B@¡B@Îâregulator-state-memô B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G&+9Ï Ri2cpclküdefault ( Òdisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G'+:Ð Ri2cpclküdefault ) Òdisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi‰ÿ G1+ ÑRspiclkapb_pclk²  ·txrxüdefault *+,-Òokayspiflash@0jedec,spi-nor‰(úð€watchdog@ff1a0000 snps,dw-wdt‰ÿ G(ìpwm@ff1b0000rockchip,rk3328-pwm‰ÿ<�Ö Rpwmpclküdefault .: Òdisabledpwm@ff1b0010rockchip,rk3328-pwm‰ÿ<�Ö Rpwmpclküdefault /: Òdisabledpwm@ff1b0020rockchip,rk3328-pwm‰ÿ <�Ö Rpwmpclküdefault 0: Òdisabledpwm@ff1b0030rockchip,rk3328-pwm‰ÿ0 G2<�Ö Rpwmpclküdefault 1: Òdisabledthermal-zonessoc-thermalE[èiè{2tripstrip-point0‹p—Єpassivetrip-point1‹L—Єpassiveû3soc-crit‹s—Ð „criticalcooling-mapsmap0¢30§ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ¶tsadc@ff250000rockchip,rk3328-tsadc‰ÿ% G:Ã$ÓÃP$ÕRtsadcapb_pclküinitdefaultsleep 45è4òB ùtsadc-apb6† )Òokay?Vû2efuse@ff260000rockchip,rk3328-efuse‰ÿ&P+> Rpclk_efuseq id@7‰cpu-leakage@17‰logic-leakage@19‰cpu-version@1a‰…ûBadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc‰ÿ( GPŠ%êRsaradcapb_pclkòV ùsaradc-apb Òdisabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450‰ÿ0TGZW]XY[\"œgpgpmmupppp0ppmmu0pp1ppmmu1‡‡ Rbuscoreòfiommu@ff330200rockchip,iommu‰ÿ3 G` œh265e_mmu“Ý Raclkiface¬ Òdisablediommu@ff340800rockchip,iommu‰ÿ4@ Gb œvepu_mmuF Raclkiface¬ Òdisabledvideo-codec@ff350000rockchip,rk3328-vpu‰ÿ5 G œvdpuF Raclkhclk¹7À8iommu@ff350800rockchip,iommu‰ÿ5@ G œvpu_mmuF Raclkiface¬À8û7iommu@ff360480rockchip,iommu ‰ÿ6€@ÿ6À@ GJ œrkvdec_mmu‹B Raclkiface¬ Òdisabledvop@ff370000rockchip,rk3328-vop‰ÿ7>ü G ‘x;Raclk_vopdclk_vophclk_vopò…†‡ ùaxiahbdclk¹9Òokayport+û endpoint@0‰ì:û?iommu@ff373f00rockchip,iommu‰ÿ7? G œvop_mmu‘; Raclkiface¬Òokayû9hdmi@ff3c0000rockchip,rk3328-dw-hdmi‰ÿ<�ìG#GçFRiahbisfrcecÎ;Óhdmiüdefault  <�=>6ÁÒokayportsportendpointì?û:codec@ff410000rockchip,rk3328-codec‰ÿAë* Rpclkmclk6ÁÒokayport@0endpointì@û phy@ff430000rockchip,rk3328-hdmi-phy‰ÿC GSäAyRsysclkrefoclkrefpclk Ÿhdmi_phy‚ÝB écpu-versionúÒokayû;clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon‰ÿD6‚øÃx=&'(ˆ‰Ž…ƒŠŒABDC"\5ˆH؉4æ$zAAA|Ó©€n6n6n6äáÀäáÀõáõáõáõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€ûsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd‰ÿE+usb2-phy@100rockchip,rk3328-usb2phy‰ARphyclk Ÿusb480m_phy‚Ã{CÒokayûCotg-portú$G;<�=œotg-bvalidotg-idlinestateÒokayûRhost-portú G> œlinestateÒokayûSdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿP@ G  =!JNRbiuciuciu-driveciu-sample),ðÑ€Òokay4>Paüdefault DEFGlHdwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿQ@ G  >"KORbiuciuciu-driveciu-sample),ðÑ€ Òdisableddwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿR@ G ?#LPRbiuciuciu-driveciu-sample),ðÑ€Òokay4>x‡üdefault  IJKl•ethernet@ff540000rockchip,rk3328-gmac‰ÿT Gœmacirq8dWXZY–ßMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macòc ùstmmaceth6ÒokayÃdfLL¢input¯ºrgmiiüdefault Mà ÞNî 'ÃP$"ethernet@ff550000rockchip,rk3328-gmac‰ÿU6 Gœmacirq8TSSU•ÞVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyòbdùstmmacethmac-phyºrmii+O Òdisabledmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22‰Vòdüdefault PQ6ûOusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2‰ÿX GMRotgHhostPbq€€@ €ÎR Óusb2-phyÒokayusb@ff5c0000 generic-ehci‰ÿ\ G NC RusbhostutmiÎSÓusbÒokayusb@ff5d0000 generic-ohci‰ÿ] G NC RusbhostutmiÎSÓusbÒokayinterrupt-controller@ff811000 arm,gic-400Š›@‰ÿÿ ÿ@ ÿ`  G ûpinctrlrockchip,rk3328-pinctrl6+@gpio0@ff210000rockchip,gpio-bank‰ÿ! G3È›Šû_gpio1@ff220000rockchip,gpio-bank‰ÿ" G4É›ŠûNgpio2@ff230000rockchip,gpio-bank‰ÿ# G5Ê›Šû%gpio3@ff240000rockchip,gpio-bank‰ÿ$ G6Ë›Špcfg-pull-up°ûVpcfg-pull-down½û^pcfg-pull-noneÌûTpcfg-pull-none-2maÌÙû]pcfg-pull-up-2ma°Ùpcfg-pull-up-4ma°ÙûWpcfg-pull-none-4maÌÙûZpcfg-pull-down-4ma½Ùpcfg-pull-none-8maÌÙûXpcfg-pull-up-8ma°ÙûYpcfg-pull-none-12maÌÙ û[pcfg-pull-up-12ma°Ù û\pcfg-output-highèpcfg-output-lowôpcfg-input-high°ÿûUpcfg-inputÿi2c0i2c0-xfer  TTû#i2c1i2c1-xfer  TTû$i2c2i2c2-xfer   TTû(i2c3i2c3-xfer  TTû)i2c3-gpio  TThdmi_i2chdmii2c-xfer  TTû=pdm-0pdmm0-clk Tûpdmm0-fsync Tpdmm0-sdi0 Tûpdmm0-sdi1 Tûpdmm0-sdi2 Tûpdmm0-sdi3 Tûpdmm0-clk-sleep Uûpdmm0-sdi0-sleep Uûpdmm0-sdi1-sleep Uûpdmm0-sdi2-sleep Uûpdmm0-sdi3-sleep Uûpdmm0-fsync-sleep Utsadcotp-gpio  Tû4otp-out  Tû5uart0uart0-xfer   VTûuart0-cts  Tûuart0-rts  Tûuart0-rts-gpio  Tuart1uart1-xfer  VTûuart1-cts Tû uart1-rts Tû!uart1-rts-gpio Tuart2-0uart2m0-xfer  VTuart2-1uart2m1-xfer  VTû"spi0-0spi0m0-clk Vspi0m0-cs0  Vspi0m0-tx  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WWWWWWWWemmcemmc-clk [ûIemmc-cmd \ûJemmc-pwren Temmc-rstnout Temmc-bus1 \emmc-bus4@ \\\\emmc-bus8€ \\\\\\\\ûKpwm0pwm0-pin Tû.pwm1pwm1-pin Tû/pwm2pwm2-pin Tû0pwmirpwmir-pin Tû1gmac-1rgmiim1-pins`  X ZZXZZZ Z ZX XZZXXX XZXXXXûMrmiim1-pins ][]]]] ] ][ [ T TTTTTgmac2phyfephyled-speed100 Tfephyled-speed10 Tfephyled-duplex Tfephyled-rxm0 Tfephyled-txm0 Tfephyled-linkm0 Tfephyled-rxm1 TûPfephyled-txm1 Tfephyled-linkm1 TûQtsadc_pintsadc-int  Ttsadc-gpio  Thdmi_pinhdmi-cec Tû<�hdmi-hpd ^û>cif-0dvp-d2d9-m0À TTTTT T T TTTTTcif-1dvp-d2d9-m1À TTTTTTTTTTTTirir-int Tûbpmicpmic-int-l Vû&usb2usb20-host-drv Tûachosenserial2:1500000n8external-gmac-clock fixed-clocksY@ Ÿgmac_clkin‚ûLsdmmc-regulatorregulator-fixed é_üdefault `zvcc_sd‰2Z ¡2Z &ûHvcc-host-5v-regulatorregulator-fixed é_üdefault a zvcc_host_5vÎâ&'vcc-host1-5v-regulatorregulator-fixed é_üdefault a zvcc_host1_5vÎâ&'vcc-sysregulator-fixedzvcc_sysÎâ‰LK@¡LK@û'ir-receivergpio-ir-receiver 1% büdefaultleds gpio-ledspower 1c7mmc0standby 1c 7heartbeatsoundaudio-graph-cardMrockchip,rk3328Sdespdif-ditlinux,spdif-ditÁportendpointìfû compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellsstatusdai-formatmclk-fsremote-endpointpinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequency#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplymmc-hs200-1_8vnon-removablevqmmc-supplyclock_in_outphy-supplyphy-modesnps,force_thresh_dma_modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dma#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpioslinux,default-triggerlabeldais