Ð þ톢8~0(r}ø&firefly,roc-rk3328-ccrockchip,rk3328 +7Firefly roc-rk3328-ccaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53‰”£x½psciËÜðûcpu@1}cpuarm,cortex-a53‰”£x½psciËÜðûcpu@2}cpuarm,cortex-a53‰”£x½psciËÜðûcpu@3}cpuarm,cortex-a53‰”£x½psciËÜðû l2-cache0cacheûopp_table0operating-points-v2ûopp-408000000Q–~ð#œ@4opp-600000000#ÃF~ð#œ@opp-8160000000£,B@#œ@opp-1008000000<ÜÈà#œ@opp-1200000000G†Œ±(#œ@opp-1296000000M?dÖ #œ@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell‰ÿ@G† Rapb_pclk^û arm-pmuarm,cortex-a53-pmu0Gdefgi display-subsystemrockchip,display-subsystem| psciarm,psci-1.0arm,psci-0.2Äsmctimerarm,armv8-timer0G   xin24m fixed-clock‚n6Ÿxin24mû?i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G)7Ri2s_clki2s_hclk² ·txrxÁ Òdisabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G*8Ri2s_clki2s_hclk²  ·txrxÁ Òdisabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G+9Ri2s_clki2s_hclk² ·txrxÁ Òdisabledspdif@ff030000rockchip,rk3328-spdif‰ÿ G.: Rmclkhclk² ·txÙdefaultç Á Òdisabledpdm@ff040000 rockchip,pdm‰ÿ=RRpdm_clkpdm_hclk² ·rxÙdefaultsleepç ñ Òdisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd‰ÿ+û5io-domains"rockchip,rk3328-io-voltage-domainÒokayû %3AOgrf-gpiorockchip,rk3328-grf-gpio\lû_power-controller!rockchip,rk3328-power-controllerx+û7pd_hevc@6‰pd_video@5‰pd_vpu@8‰Freboot-modesyscon-reboot-modeŒÈ“RBßRBíRBà ½RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G7&ÒRbaudclkapb_pclk²  ·txrxÙdefault çÉÖ Òdisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G8'ÓRbaudclkapb_pclk²  ·txrxÙdefault ç ÉÖ Òdisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G9(ÔRbaudclkapb_pclk²  ·txrxÙdefaultç!ÉÖÒokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G$+7Í Ri2cpclkÙdefaultç" Òdisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G%+8Î Ri2cpclkÙdefaultç#Òokaypmic@18rockchip,rk805‰ $G‚Ÿxin32krk805-clkout2\lÙdefaultç%à&&'&3&?KûbregulatorsDCDC_REG1 Wvdd_logicf ß4~ –ªregulator-state-mem¼ÔB@DCDC_REG2Wvdd_armf ß4~ –ªûregulator-state-mem¼Ô~ðDCDC_REG3Wvcc_ddr–ªregulator-state-mem¼DCDC_REG4Wvcc_iof2Z ~2Z –ªûregulator-state-mem¼Ô2Z LDO_REG1Wvcc_18fw@~w@–ªûregulator-state-mem¼Ôw@LDO_REG2 Wvcc18_emmcfw@~w@–ªûregulator-state-mem¼Ôw@LDO_REG3Wvdd_10fB@~B@–ªregulator-state-mem¼ÔB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G&+9Ï Ri2cpclkÙdefaultç' Òdisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G'+:Ð Ri2cpclkÙdefaultç( Òdisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi‰ÿ G1+ ÑRspiclkapb_pclk²  ·txrxÙdefaultç)*+, Òdisabledwatchdog@ff1a0000 snps,dw-wdt‰ÿ G(ìpwm@ff1b0000rockchip,rk3328-pwm‰ÿ<�Ö RpwmpclkÙdefaultç-ð Òdisabledpwm@ff1b0010rockchip,rk3328-pwm‰ÿ<�Ö RpwmpclkÙdefaultç.ð Òdisabledpwm@ff1b0020rockchip,rk3328-pwm‰ÿ <�Ö RpwmpclkÙdefaultç/ð Òdisabledpwm@ff1b0030rockchip,rk3328-pwm‰ÿ0 G2<�Ö RpwmpclkÙdefaultç0ð Òdisabledthermal-zonessoc-thermalûèè11tripstrip-point0ApMЄpassivetrip-point1ALMЄpassiveû2soc-critAsMÐ „criticalcooling-mapsmap0X20]ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿltsadc@ff250000rockchip,rk3328-tsadc‰ÿ% G:y$‰ÃP$ÕRtsadcapb_pclkÙinitdefaultsleepç3ñ4ž3¨B ¯tsadc-apb»5Ȇ ßÒokayû1efuse@ff260000rockchip,rk3328-efuse‰ÿ&P+> Rpclk_efuseõ id@7‰cpu-leakage@17‰logic-leakage@19‰cpu-version@1a‰ û@adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc‰ÿ( GP%êRsaradcapb_pclk¨V ¯saradc-apb Òdisabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450‰ÿ0TGZW]XY[\" gpgpmmupppp0ppmmu0pp1ppmmu1‡‡ Rbuscore¨fiommu@ff330200rockchip,iommu‰ÿ3 G`  h265e_mmu“Ý Raclkiface0 Òdisablediommu@ff340800rockchip,iommu‰ÿ4@ Gb  vepu_mmuF Raclkiface0 Òdisabledvideo-codec@ff350000rockchip,rk3328-vpu‰ÿ5 G  vdpuF Raclkhclk=6D7iommu@ff350800rockchip,iommu‰ÿ5@ G  vpu_mmuF Raclkiface0D7û6iommu@ff360480rockchip,iommu ‰ÿ6€@ÿ6À@ GJ  rkvdec_mmu‹B Raclkiface0 Òdisabledvop@ff370000rockchip,rk3328-vop‰ÿ7>ü G ‘x;Raclk_vopdclk_vophclk_vop¨…†‡ ¯axiahbdclk=8Òokayport+û endpoint@0‰R9û>iommu@ff373f00rockchip,iommu‰ÿ7? G  vop_mmu‘; Raclkiface0Òokayû8hdmi@ff3c0000rockchip,rk3328-dw-hdmi‰ÿ<�ÉG#GçFRiahbisfrcecb:ghdmiÙdefault ç;<�=»5ÁÒokayportsportendpointR>û9codec@ff410000rockchip,rk3328-codec‰ÿAë* Rpclkmclk»5Á Òdisabledphy@ff430000rockchip,rk3328-hdmi-phy‰ÿC GSä?yRsysclkrefoclkrefpclk Ÿhdmi_phy‚q@ }cpu-versionŽÒokayû:clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon‰ÿD»5‚™øyx=&'(ˆ‰Ž…ƒŠŒABDC"\5ˆH؉4æ$¦z???|‰©€n6n6n6äáÀäáÀõáõáõáõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€ûsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd‰ÿE+usb2-phy@100rockchip,rk3328-usb2phy‰?Rphyclk Ÿusb480m_phy‚y{¦AÒokayûAotg-portŽ$G;<�= otg-bvalidotg-idlinestateÒokayûPhost-portŽ G>  linestateÒokayûQdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿP@ G  =!JNRbiuciuciu-driveciu-sample½ÈðÑ€ÒokayÖàòÙdefaultçBCDE(5CFOdwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿQ@ G  >"KORbiuciuciu-driveciu-sample½ÈðÑ€ Òdisableddwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿR@ G ?#LPRbiuciuciu-driveciu-sample½ÈðÑ€ÒokayÖà\ixÙdefault çGHICOethernet@ff540000rockchip,rk3328-gmac‰ÿT G macirq8dWXZY–ßMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac¨c ¯stmmaceth»5Òokayydf¦JJ†input“KžrgmiiÙdefaultçL§ °$À Ö'ÃPëö$ ethernet@ff550000rockchip,rk3328-gmac‰ÿU»5 G macirq8TSSU•ÞVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy¨bd¯stmmacethmac-phyžrmiiM Òdisabledmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22‰V¨dÙdefaultçNOûMusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2‰ÿX GMRotg0otg8JY€€@ hbP gusb2-phyÒokayusb@ff5c0000 generic-ehci‰ÿ\ G NA RusbhostutmibQgusbÒokayusb@ff5d0000 generic-ohci‰ÿ] G NA RusbhostutmibQgusbÒokayinterrupt-controller@ff811000 arm,gic-400rƒ@‰ÿÿ ÿ@ ÿ`  G ûpinctrlrockchip,rk3328-pinctrl»5+@gpio0@ff210000rockchip,gpio-bank‰ÿ! G3È\lƒrû]gpio1@ff220000rockchip,gpio-bank‰ÿ" G4É\lƒrû$gpio2@ff230000rockchip,gpio-bank‰ÿ# G5Ê\lƒrgpio3@ff240000rockchip,gpio-bank‰ÿ$ G6Ë\lƒrpcfg-pull-up˜ûTpcfg-pull-down¥û\pcfg-pull-none´ûRpcfg-pull-none-2ma´Áû[pcfg-pull-up-2ma˜Ápcfg-pull-up-4ma˜ÁûUpcfg-pull-none-4ma´ÁûXpcfg-pull-down-4ma¥Ápcfg-pull-none-8ma´ÁûVpcfg-pull-up-8ma˜ÁûWpcfg-pull-none-12ma´Á ûYpcfg-pull-up-12ma˜Á ûZpcfg-output-highÐpcfg-output-lowÜpcfg-input-high˜çûSpcfg-inputçi2c0i2c0-xfer ôRRû"i2c1i2c1-xfer ôRRû#i2c2i2c2-xfer ô RRû'i2c3i2c3-xfer ôRRû(i2c3-gpio ôRRhdmi_i2chdmii2c-xfer ôRRû<�pdm-0pdmm0-clkôRû pdmm0-fsyncôRpdmm0-sdi0ôRûpdmm0-sdi1ôRûpdmm0-sdi2ôRûpdmm0-sdi3ôRûpdmm0-clk-sleepôSûpdmm0-sdi0-sleepôSûpdmm0-sdi1-sleepôSûpdmm0-sdi2-sleepôSûpdmm0-sdi3-sleepôSûpdmm0-fsync-sleepôStsadcotp-gpioô Rû3otp-outô Rû4uart0uart0-xfer ô TRûuart0-ctsô Rûuart0-rtsô Rûuart0-rts-gpioô Ruart1uart1-xfer ôTRûuart1-ctsôRûuart1-rtsôRû uart1-rts-gpioôRuart2-0uart2m0-xfer ôTRuart2-1uart2m1-xfer ôTRû!spi0-0spi0m0-clkôTspi0m0-cs0ô Tspi0m0-txô Tspi0m0-rxô Tspi0m0-cs1ô Tspi0-1spi0m1-clkôTspi0m1-cs0ôTspi0m1-txôTspi0m1-rxôTspi0m1-cs1ôTspi0-2spi0m2-clkôTû)spi0m2-cs0ôTû,spi0m2-txôTû*spi0m2-rxôTû+i2s1i2s1-mclkôRi2s1-sclkôRi2s1-lrckrxôRi2s1-lrcktxôRi2s1-sdiôRi2s1-sdoôRi2s1-sdio1ôRi2s1-sdio2ôRi2s1-sdio3ôRi2s1-sleepôSSSSSSSSSi2s2-0i2s2m0-mclkôRi2s2m0-sclkôRi2s2m0-lrckrxôRi2s2m0-lrcktxôRi2s2m0-sdiôRi2s2m0-sdoôRi2s2m0-sleep`ôSSSSSSi2s2-1i2s2m1-mclkôRi2s2m1-sclkôRi2sm1-lrckrxôRi2s2m1-lrcktxôRi2s2m1-sdiôRi2s2m1-sdoôRi2s2m1-sleepPôSSSSSspdif-0spdifm0-txôRspdif-1spdifm1-txôRspdif-2spdifm2-txôRû sdmmc0-0sdmmc0m0-pwrenôUsdmmc0m0-gpioôUsdmmc0-1sdmmc0m1-pwrenôUsdmmc0m1-gpioôUû^sdmmc0sdmmc0-clkôVûBsdmmc0-cmdôWûCsdmmc0-dectnôUûDsdmmc0-wrprtôUsdmmc0-bus1ôWsdmmc0-bus4@ôWWWWûEsdmmc0-gpio€ôUUUUUUUUsdmmc0extsdmmc0ext-clkôXsdmmc0ext-cmdôUsdmmc0ext-wrprtôUsdmmc0ext-dectnôUsdmmc0ext-bus1ôUsdmmc0ext-bus4@ôUUUUsdmmc0ext-gpio€ôUUUUUUUUsdmmc1sdmmc1-clkô Vsdmmc1-cmdô Wsdmmc1-pwrenôWsdmmc1-wrprtôWsdmmc1-dectnôWsdmmc1-bus1ôWsdmmc1-bus4@ôWWWWsdmmc1-gpioô U UUUUUUUUemmcemmc-clkôYûGemmc-cmdôZûHemmc-pwrenôRemmc-rstnoutôRemmc-bus1ôZemmc-bus4@ôZZZZemmc-bus8€ôZZZZZZZZûIpwm0pwm0-pinôRû-pwm1pwm1-pinôRû.pwm2pwm2-pinôRû/pwmirpwmir-pinôRû0gmac-1rgmiim1-pins`ô V XXVXXX X XV VXXVVV VXVVVVûLrmiim1-pinsô[Y[[[[ [ [Y Y R RRRRRgmac2phyfephyled-speed100ôRfephyled-speed10ôRfephyled-duplexôRfephyled-rxm0ôRfephyled-txm0ôRfephyled-linkm0ôRfephyled-rxm1ôRûNfephyled-txm1ôRfephyled-linkm1ôRûOtsadc_pintsadc-intô Rtsadc-gpioô Rhdmi_pinhdmi-cecôRû;hdmi-hpdô\û=cif-0dvp-d2d9-m0ÀôRRRRR R R RRRRRcif-1dvp-d2d9-m1ÀôRRRRRRRRRRRRpmicpmic-int-lôTû%usb2usb20-host-drvôRû`chosenserial2:1500000n8external-gmac-clock fixed-clocksY@ Ÿgmac_clkin‚ûJdc-12vregulator-fixedWdc_12v–ªf·~·ûasdmmc-regulatorregulator-fixed »]Ùdefaultç^Wvcc_sdf2Z ~2Z ûFsdmmcio-regulatorregulator-gpio _w@2Z  Wvcc_sdio&voltagefw@~2Z –&ûvcc-host1-5v-regulatorregulator-fixed5 »$Ùdefaultç` Wvcc_host1_5v–&vcc-sysregulator-fixedWvcc_sys–ªfLK@~LK@aû&vcc-phy-regulatorregulator-fixedWvcc_phy–ªûKleds gpio-ledspowerHfirefly:blue:power Nheartbeat bdon¢#userHfirefly:yellow:userNmmc1 bdoff¢ compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellsstatuspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removableclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpblsnps,txpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dma#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpiosstatesregulator-typeenable-active-highlabellinux,default-triggerdefault-state