Ð þíY8z(Ayà$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53‰”£x½psciËÜðûcpu@1}cpuarm,cortex-a53‰”£x½psciËÜûcpu@2}cpuarm,cortex-a53‰”£x½psciËÜûcpu@3}cpuarm,cortex-a53‰”£x½psciËÜû l2-cache0cacheûopp_table0operating-points-v2ûopp-408000000Q–~ð#œ@4opp-600000000#ÃF~ð#œ@opp-8160000000£,B@#œ@opp-1008000000<ÜÈà#œ@opp-1200000000G†Œ±(#œ@opp-1296000000M?dÖ #œ@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell‰ÿ@G† Rapb_pclk^û arm-pmuarm,cortex-a53-pmu0Gdefgi display-subsystemrockchip,display-subsystem| psciarm,psci-1.0arm,psci-0.2Äsmctimerarm,armv8-timer0G   xin24m fixed-clock‚n6Ÿxin24mû<�i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G)7Ri2s_clki2s_hclk² ·txrxÁ Òdisabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G*8Ri2s_clki2s_hclk²  ·txrxÁ Òdisabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ G+9Ri2s_clki2s_hclk² ·txrxÁ Òdisabledspdif@ff030000rockchip,rk3328-spdif‰ÿ G.: Rmclkhclk² ·txÙdefaultç Á Òdisabledpdm@ff040000 rockchip,pdm‰ÿ=RRpdm_clkpdm_hclk² ·rxÙdefaultsleepç ñ Òdisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd‰ÿ+û2io-domains"rockchip,rk3328-io-voltage-domain Òdisabledgrf-gpiorockchip,rk3328-grf-gpioû power-controller!rockchip,rk3328-power-controller+û4pd_hevc@6‰pd_video@5‰pd_vpu@8‰Freboot-modesyscon-reboot-mode+È2RBÃ>RBÃLRBà \RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G7&ÒRbaudclkapb_pclk²  ·txrxÙdefault çhu Òdisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G8'ÓRbaudclkapb_pclk²  ·txrxÙdefault çhu Òdisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ G9(ÔRbaudclkapb_pclk²  ·txrxÙdefaultçhuÒokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G$+7Í Ri2cpclkÙdefaultç Òdisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G%+8Î Ri2cpclkÙdefaultçÒokaypmic@18rockchip,rk805‰ G‚Ÿxin32krk805-clkout2û Ùdefaultç! ®"º"Æ"Ò"Þ#ê#regulatorsDCDC_REG1 övdd_logic ß4 5Iregulator-state-mem[sB@DCDC_REG2övdd_arm ß4 5Iûregulator-state-mem[s~ðDCDC_REG3övcc_ddr5Iregulator-state-mem[DCDC_REG4övcc_io2Z 2Z 5Iû#regulator-state-mem[s2Z LDO_REG1övcc_18w@w@5Iregulator-state-mem[sw@LDO_REG2 övcc18_emmcw@w@5Iregulator-state-mem[sw@LDO_REG3övdd_10B@B@5Iregulator-state-mem[sB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G&+9Ï Ri2cpclkÙdefaultç$ Òdisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ G'+:Ð Ri2cpclkÙdefaultç% Òdisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi‰ÿ G1+ ÑRspiclkapb_pclk²  ·txrxÙdefaultç&'() Òdisabledwatchdog@ff1a0000 snps,dw-wdt‰ÿ G(ìpwm@ff1b0000rockchip,rk3328-pwm‰ÿ<�Ö RpwmpclkÙdefaultç* Òdisabledpwm@ff1b0010rockchip,rk3328-pwm‰ÿ<�Ö RpwmpclkÙdefaultç+ Òdisabledpwm@ff1b0020rockchip,rk3328-pwm‰ÿ <�Ö RpwmpclkÙdefaultç, Òdisabledpwm@ff1b0030rockchip,rk3328-pwm‰ÿ0 G2<�Ö RpwmpclkÙdefaultç- Òdisabledthermal-zonessoc-thermalš°è¾èÐ.tripstrip-point0àpìЄpassivetrip-point1àLìЄpassiveû/soc-critàsìÐ „criticalcooling-mapsmap0÷/0üÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ tsadc@ff250000rockchip,rk3328-tsadc‰ÿ% G:$(ÃP$ÕRtsadcapb_pclkÙinitdefaultsleepç0ñ1=0GB Ntsadc-apbZ2g† ~Òokayû.efuse@ff260000rockchip,rk3328-efuse‰ÿ&P+> Rpclk_efuse” id@7‰cpu-leakage@17‰logic-leakage@19‰cpu-version@1a‰¨û=adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc‰ÿ( GP­%êRsaradcapb_pclkGV Nsaradc-apb Òdisabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450‰ÿ0TGZW]XY[\"¿gpgpmmupppp0ppmmu0pp1ppmmu1‡‡ RbuscoreGfiommu@ff330200rockchip,iommu‰ÿ3 G` ¿h265e_mmu“Ý RaclkifaceÏ Òdisablediommu@ff340800rockchip,iommu‰ÿ4@ Gb ¿vepu_mmuF RaclkifaceÏ Òdisabledvideo-codec@ff350000rockchip,rk3328-vpu‰ÿ5 G ¿vdpuF RaclkhclkÜ3ã4iommu@ff350800rockchip,iommu‰ÿ5@ G ¿vpu_mmuF RaclkifaceÏã4û3iommu@ff360480rockchip,iommu ‰ÿ6€@ÿ6À@ GJ ¿rkvdec_mmu‹B RaclkifaceÏ Òdisabledvop@ff370000rockchip,rk3328-vop‰ÿ7>ü G ‘x;Raclk_vopdclk_vophclk_vopG…†‡ NaxiahbdclkÜ5 Òdisabledport+û endpoint@0‰ñ6û;iommu@ff373f00rockchip,iommu‰ÿ7? G ¿vop_mmu‘; RaclkifaceÏ Òdisabledû5hdmi@ff3c0000rockchip,rk3328-dw-hdmi‰ÿ<�hG#GçFRiahbisfrcec7hdmiÙdefault ç89:Z2Á Òdisabledportsportendpointñ;û6codec@ff410000rockchip,rk3328-codec‰ÿAë* RpclkmclkZ2Á Òdisabledphy@ff430000rockchip,rk3328-hdmi-phy‰ÿC GSä<�yRsysclkrefoclkrefpclk Ÿhdmi_phy‚= cpu-version- Òdisabledû7clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon‰ÿDZ2‚8øx=&'(ˆ‰Ž…ƒŠŒABDC"\5ˆH؉4æ$Ez<�<�<�|(©€n6n6n6äáÀäáÀõáõáõáõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€ûsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd‰ÿE+usb2-phy@100rockchip,rk3328-usb2phy‰<�Rphyclk Ÿusb480m_phy‚{E>Òokayû>otg-port-$G;<�=¿otg-bvalidotg-idlinestateÒokayûOhost-port- G> ¿linestateÒokayûPdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿP@ G  =!JNRbiuciuciu-driveciu-sample\gðÑ€Òokayu‘¢Ùdefaultç?@AB­Cdwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿQ@ G  >"KORbiuciuciu-driveciu-sample\gðÑ€Òokayu‘¹ÆÜDçÙdefault çEFGdwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿR@ G ?#LPRbiuciuciu-driveciu-sample\gðÑ€ÒokayuçÙdefault çHIJethernet@ff540000rockchip,rk3328-gmac‰ÿT G¿macirq8dWXZY–ßMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macGc NstmmacethZ2 Òdisabledethernet@ff550000rockchip,rk3328-gmac‰ÿUZ2 G¿macirq8TSSU•ÞVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyGbdNstmmacethmac-phyõrmiiþKÒokay Loutpute!úð€ETmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22‰VGdÙdefaultçMN5ûKusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2‰ÿX GMRotgGotgOap€€@ O usb2-phyÒokayusb@ff5c0000 generic-ehci‰ÿ\ G N> RusbhostutmiPusbÒokayusb@ff5d0000 generic-ohci‰ÿ] G N> RusbhostutmiPusbÒokayinterrupt-controller@ff811000 arm,gic-400‰š@‰ÿÿ ÿ@ ÿ`  G ûpinctrlrockchip,rk3328-pinctrlZ2+@gpio0@ff210000rockchip,gpio-bank‰ÿ! G3Èû š‰û^gpio1@ff220000rockchip,gpio-bank‰ÿ" G4Éû š‰û]gpio2@ff230000rockchip,gpio-bank‰ÿ# G5Êû š‰û gpio3@ff240000rockchip,gpio-bank‰ÿ$ G6Ëû š‰pcfg-pull-up¯ûSpcfg-pull-down¼û[pcfg-pull-noneËûQpcfg-pull-none-2maËØûZpcfg-pull-up-2ma¯Øpcfg-pull-up-4ma¯ØûTpcfg-pull-none-4maËØûWpcfg-pull-down-4ma¼Øpcfg-pull-none-8maËØûUpcfg-pull-up-8ma¯ØûVpcfg-pull-none-12maËØ ûXpcfg-pull-up-12ma¯Ø ûYpcfg-output-highçpcfg-output-lowópcfg-input-high¯þûRpcfg-inputþi2c0i2c0-xfer  QQûi2c1i2c1-xfer  QQûi2c2i2c2-xfer   QQû$i2c3i2c3-xfer  QQû%i2c3-gpio  QQhdmi_i2chdmii2c-xfer  QQû9pdm-0pdmm0-clk Qû pdmm0-fsync Qpdmm0-sdi0 Qûpdmm0-sdi1 Qûpdmm0-sdi2 Qûpdmm0-sdi3 Qûpdmm0-clk-sleep Rûpdmm0-sdi0-sleep Rûpdmm0-sdi1-sleep Rûpdmm0-sdi2-sleep Rûpdmm0-sdi3-sleep Rûpdmm0-fsync-sleep Rtsadcotp-gpio  Qû0otp-out  Qû1uart0uart0-xfer   SQûuart0-cts  Qûuart0-rts  Qûuart0-rts-gpio  Quart1uart1-xfer  SQûuart1-cts Qûuart1-rts Qûuart1-rts-gpio Quart2-0uart2m0-xfer  SQuart2-1uart2m1-xfer  SQûspi0-0spi0m0-clk Sspi0m0-cs0  Sspi0m0-tx  Sspi0m0-rx  Sspi0m0-cs1  Sspi0-1spi0m1-clk Sspi0m1-cs0 Sspi0m1-tx Sspi0m1-rx Sspi0m1-cs1 Sspi0-2spi0m2-clk Sû&spi0m2-cs0 Sû)spi0m2-tx Sû'spi0m2-rx Sû(i2s1i2s1-mclk Qi2s1-sclk Qi2s1-lrckrx Qi2s1-lrcktx Qi2s1-sdi Qi2s1-sdo Qi2s1-sdio1 Qi2s1-sdio2 Qi2s1-sdio3 Qi2s1-sleep RRRRRRRRRi2s2-0i2s2m0-mclk Qi2s2m0-sclk Qi2s2m0-lrckrx Qi2s2m0-lrcktx Qi2s2m0-sdi Qi2s2m0-sdo Qi2s2m0-sleep` RRRRRRi2s2-1i2s2m1-mclk Qi2s2m1-sclk Qi2sm1-lrckrx Qi2s2m1-lrcktx Qi2s2m1-sdi Qi2s2m1-sdo Qi2s2m1-sleepP RRRRRspdif-0spdifm0-tx Qspdif-1spdifm1-tx Qspdif-2spdifm2-tx Qû sdmmc0-0sdmmc0m0-pwren Tsdmmc0m0-gpio Tsdmmc0-1sdmmc0m1-pwren Tsdmmc0m1-gpio Tû_sdmmc0sdmmc0-clk Uû?sdmmc0-cmd Vû@sdmmc0-dectn TûAsdmmc0-wrprt Tsdmmc0-bus1 Vsdmmc0-bus4@ VVVVûBsdmmc0-gpio€ TTTTTTTTsdmmc0extsdmmc0ext-clk Wsdmmc0ext-cmd Tsdmmc0ext-wrprt Tsdmmc0ext-dectn Tsdmmc0ext-bus1 Tsdmmc0ext-bus4@ TTTTsdmmc0ext-gpio€ TTTTTTTTsdmmc1sdmmc1-clk  UûGsdmmc1-cmd  VûFsdmmc1-pwren Vsdmmc1-wrprt Vsdmmc1-dectn Vsdmmc1-bus1 Vsdmmc1-bus4@ VVVVûEsdmmc1-gpio  T TTTTTTTTemmcemmc-clk XûHemmc-cmd YûIemmc-pwren Qemmc-rstnout Qemmc-bus1 Yemmc-bus4@ YYYYemmc-bus8€ YYYYYYYYûJpwm0pwm0-pin Qû*pwm1pwm1-pin Qû+pwm2pwm2-pin Qû,pwmirpwmir-pin Qû-gmac-1rgmiim1-pins`  U WWUWWW W WU UWWUUU UWUUUUrmiim1-pins ZXZZZZ Z ZX X Q QQQQQgmac2phyfephyled-speed100 Qfephyled-speed10 Qfephyled-duplex Qfephyled-rxm0 Qfephyled-txm0 Qfephyled-linkm0 Qfephyled-rxm1 QûMfephyled-txm1 Qfephyled-linkm1 QûNtsadc_pintsadc-int  Qtsadc-gpio  Qhdmi_pinhdmi-cec Qû8hdmi-hpd [û:cif-0dvp-d2d9-m0À QQQQQ Q Q QQQQQcif-1dvp-d2d9-m1À QQQQQQQQQQQQpmicpmic-int-l Sû!sdio-pwrseqwifi-enable-h Qû\chosenserial2:1500000n8dc-12vregulator-fixedödc_12v5I··û`sdio-pwrseqmmc-pwrseq-simpleÙdefaultç\ %]ûDsdmmc-regulatorregulator-fixed 1^Ùdefaultç_övcc_sd2Z 2Z 6#ûCvcc-sysregulator-fixedövcc_sys5ILK@LK@6`û"vcc-phy-regulatorregulator-fixedövcc_phy5IûL compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellsstatuspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablephy-modephy-handlephy-supplyclock_in_outassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dma#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply