Ð þí}Ý8uè(õu°$mediatek,mt8173-evbmediatek,mt8173 +!7MediaTek MT8173 evaluation boardaliases=/soc/ovl@1400c000B/soc/ovl@1400d000G/soc/rdma@1400e000M/soc/rdma@1400f000S/soc/rdma@14010000Y/soc/wdma@14011000_/soc/wdma@14012000e/soc/color@14013000l/soc/color@14014000s/soc/split@14018000z/soc/split@14019000/soc/dpi@1401d000†/soc/dsi@1401b000‹/soc/dsi@1401c000/soc/rdma@14001000š/soc/rdma@14002000¤/soc/rsz@14003000­/soc/rsz@14004000¶/soc/rsz@14005000¿/soc/wdma@14006000É/soc/wrot@14007000Ó/soc/wrot@14008000Ý/soc/serial@11002000å/soc/serial@11003000í/soc/serial@11004000õ/soc/serial@11005000opp_table0operating-points-v2ý opp-50700000084À xopp-702000000)׫€ Úàopp-1001000000;ª @ÿØopp-1105000000AÜö@ehopp-1209000000Hà@Çopp-1300000000M|m èopp-1508000000YâAìopp-1703000000e·À*ˆopp_table1operating-points-v2ý opp-50700000084À ¢`opp-702000000)׫€ :¸opp-1001000000;ª @%opp-1209000000Hà@Å@opp-1404000000S¯W]˜opp-1612000000`+¨opp-1807000000k´¡Àèopp-2106000000}‡€*ˆcpus+cpu-mapcluster0core0%core1%cluster1core0%core1%cpu@0)cpuarm,cortex-a5359psciGWf mcpuintermediatey  cpu@1)cpuarm,cortex-a5359psciGWf mcpuintermediatey  cpu@100)cpuarm,cortex-a7259psciGWfmcpuintermediatey  ™ cpu@101)cpuarm,cortex-a7259psciGWfmcpuintermediatey  ™ idle-states¥pscicpu-sleep-0arm,idle-state²ÃÔ¨ä@õpmu_a53arm,cortex-a53-pmu  pmu_a72arm,cortex-a72-pmu  psci#arm,psci-1.0arm,psci-0.2arm,psci@smc*„6„>„oscillator@0 fixed-clockERŒº€bclk26moscillator@1 fixed-clockER}bclk32koscillator@2 fixed-clockERbcpum_ckthermal-zonescpu_thermaluè‹è™©Ütripstrip-point@0»  ÇÐ0passivetrip-point@1»LÇÐ0passivecpu_crit@0»Á8ÇÐ 0criticalcooling-mapsmap@0Ò×æ map@1Ò×æreserved-memory+óvpu_dma_mem_regionshared-dma-pool5·Pútimerarm,armv8-timer 0    soc+ simple-busóclock-controller@10000000mediatek,mt8173-topckgen5Epower-controller@10001000 mediatek,mt8173-infracfgsyscon5E power-controller@10003000mediatek,mt8173-pericfgsyscon50E syscfg_pctl_a@10005000%mediatek,mt8173-pctl-a-syscfgsyscon5Ppinctrl@10005000mediatek,mt8173-pinctrl5°-?O[p$ ‘’“xxx@pins1ˆ•i2c0pins1-.¤i2c1pins1}~¤i2c2 pins1+,¤i2c3$pins1jk¤i2c4%pins1…†¤i2c6&pins1de¤disp_pwm0_pins>pins1W±mmc0default'pins_cmd_dat$9:;<=>?@Bˆ¼pins_clkA•pins_rstD¼mmc1default+pins_cmd_datIJKLNˆÉ¼fpins_clkM•Épins_insert„¼mmc0(pins_cmd_dat$9:;<=>?@BˆÉ¼epins_clkAÉ•epins_rstD¼mmc1,pins_cmd_datIJKLNˆÉ¼fpins_clkMÉ•fusb_iddig_pull_up5pins_iddig¼usb_iddig_pull_down6pins_iddig•spi0!pins_spiEFGHscpsys@10006000mediatek,mt8173-scpsysØ5`fUXimmfgmmvencvenc_ltìwatchdog@10007000(mediatek,mt8173-wdtmediatek,mt6589-wdt5ptimer@10008000,mediatek,mt8173-timermediatek,mt6577-timer5€  f xpwrap@1000d000mediatek,mt8173-pwrap5Ðõpwrap  ™ÿpwrapf   mspiwrapmt6397mediatek,mt6397  [pmt6397regulatormediatek,mt6397-regulatorbuck_vpca15  buck_vpca155vpca15D ®`\™pt0Ô‰ buck_vpca7  buck_vpca75vpca7D ®`\™pt0ԝsbuck_vsramca15 buck_vsramca15 5vsramca15D ®`\™pt0Ô‰buck_vsramca7 buck_vsramca7 5vsramca7D ®`\™pt0Ô‰ buck_vcore  buck_vcore5vcoreD ®`\™pt0Ô‰buck_vgpu  buck_vgpu5vgpuD ®`\™pt0ԝsbuck_vdrm  buck_vdrm5vdrmDO€\\Àt0Ô‰buck_vio18  buck_vio185vio18D¸ \6`t0Ô‰*ldo_vtcxo  ldo_vtcxo5vtcxo‰ldo_va28  ldo_va285va28‰ldo_vcama  ldo_vcama5vcamaDã`\*¹€Úldo_vio28  ldo_vio285vio28‰ldo_vusb  ldo_vusb5vusb2ldo_vmc ldo_vmc5vmcDw@\2Z Ú.ldo_vmch  ldo_vmch5vmchD-ÆÀ\2Z Ú-ldo_vemc3v3  ldo_vemc3v3 5vemc_3v3D-ÆÀ\2Z Ú)ldo_vgp1  ldo_vgp15vcamdD \2Z ðldo_vgp2  ldo_vgp25vcamioDB@\2Z Úldo_vgp3  ldo_vgp35vcamafDO€\2Z Úldo_vgp4  ldo_vgp45vgp4DO€\2Z Úldo_vgp5  ldo_vgp55vgp5DO€\-ÆÀÚldo_vgp6  ldo_vgp65vgp6DO€\2Z Úldo_vibr  ldo_vibr5vibrDÖ \2Z Úcec@10013000mediatek,mt8173-cec50¼  §f ¹okayvpu@10020000mediatek,mt8173-vpu 5 õtcmcfg_reg  ¦fgmmainÀ:intpol-controller@10200620.mediatek,mt8173-sysirqmediatek,mt6577-sysirq[p 5  iommu@10205000mediatek,mt8173-m4u5 P  ‹fmbclkÎÝ9efuse@10206000mediatek,mt8173-efuse5 `+calib@5285( #clock-controller@10209000mediatek,mt8173-apmixedsys5 Ehdmi-phy@10209100mediatek,mt8173-hdmi-phy5 ‘$fmpll_refbhdmitx_dig_ctsê ùE ¹okayAmailbox@10212000mediatek,mt8173-gce5!   ‡fmgcemipi-dphy@10215000mediatek,mt8173-mipi-tx5!Pf bmipi_tx0_pllE  ¹disabled;mipi-dphy@10216000mediatek,mt8173-mipi-tx5!`f bmipi_tx1_pllE  ¹disabled<�interrupt-controller@10220000 arm,gic-400p [@5"" "@ "`    auxadc@11001000mediatek,mt8173-auxadc5fmmain""serial@11002000*mediatek,mt8173-uartmediatek,mt6577-uart5   Sf$ mbaudbus¹okayserial@11003000*mediatek,mt8173-uartmediatek,mt6577-uart50  Tf% mbaudbus ¹disabledserial@11004000*mediatek,mt8173-uartmediatek,mt6577-uart5@  Uf& mbaudbus ¹disabledserial@11005000*mediatek,mt8173-uartmediatek,mt6577-uart5P  Vf' mbaudbus ¹disabledi2c@11007000mediatek,mt8173-i2c 5pp€  L4f  mmaindma>defaultL+ ¹disabledi2c@11008000mediatek,mt8173-i2c 5€p€€  M4f  mmaindma>defaultL+¹okayda9211@68 dlg,da92115hregulatorsBUCKA5VBUCKAD ®`\ý0V„€mC#€t'‰ BUCKB5VBUCKBD ®`\ý0V„€m-ÆÀt'i2c@11009000mediatek,mt8173-i2c 5p€  N4f  mmaindma>defaultL + ¹disabledspi@1100a000mediatek,mt8173-spi+5   nf4\mparent-clksel-clkspi-clk¹okay>defaultL!„thermal@1100b000˜mediatek,mt8173-thermal5°  Ff mthermauxadcÿ®"¾Ò#Þcalibration-dataspi@1100d000mediatek,mt8173-nor5Ðàf!rmspisf+ ¹disabledi2c@11010000mediatek,mt8173-i2c 5p€€  O4f  mmaindma>defaultL$+ ¹disabledi2c@11011000mediatek,mt8173-i2c 5p€  P4f  mmaindma>defaultL%+ ¹disabledi2c@11012000mediatek,mt8173-hdmi-ddc  Q5 fmddc-i2ci2c@11013000mediatek,mt8173-i2c 50p€€  R4f#  mmaindma>defaultL&+ ¹disabledaudio-controller@11220000mediatek,mt8173-afe-pcm5"  †Pfdey…†‡ˆ‰bminfra_sys_audio_clktop_pdn_audiotop_pdn_aud_intbusbck0bck1i2s0_mi2s1_mi2s2_mi2s3_mi2s3_bïmnÿmmc@11230000mediatek,mt8173-mmc5#  Gf_ msourcehclk¹okay>defaultstate_uhsL'( *úð€8Jg„§)³*Àmmc@11240000mediatek,mt8173-mmc5$  HfR msourcehclk¹okay>defaultstate_uhsL+, *úð€Îß ì„§-³.mmc@11250000mediatek,mt8173-mmc5%  IfR msourcehclk ¹disabledmmc@11260000mediatek,mt8173-mmc5&  Jfu msourcehclk ¹disabledusb@11271000mediatek,mt8173-mtu3 5'0( õmacippc  @õ/01 f^msys_ckref_ck ú+ó¹okay23+42otg:>defaultid_floatid_groundL55H6xhci@11270000mediatek,mt8173-xhci5'õmac  s f^msys_ckref_ck¹okay27usb-phy@11290000mediatek,mt8173-u3phy5)+ó¹okayusb-phy@112908005)fmref ¹okay/usb-phy@112909005) fmref ¹okay0usb-phy@112910005)fmref ¹okay1clock-controller@14000000mediatek,mt8173-mmsyssyscon5ïURׄE8rdma@14001000-mediatek,mt8173-mdp-rdmamediatek,mt8173-mdp5f88g9n|:rdma@14002000mediatek,mt8173-mdp-rdma5 f88g9„nrsz@14003000mediatek,mt8173-mdp-rsz50f8rsz@14004000mediatek,mt8173-mdp-rsz5@f8rsz@14005000mediatek,mt8173-mdp-rsz5Pf8wdma@14006000mediatek,mt8173-mdp-wdma5`f8 g9nwrot@14007000mediatek,mt8173-mdp-wrot5pf8 g9nwrot@14008000mediatek,mt8173-mdp-wrot5€f8 g9…novl@1400c000mediatek,mt8173-disp-ovl5À  ´f8g9novl@1400d000mediatek,mt8173-disp-ovl5Ð  µf8g9€nrdma@1400e000mediatek,mt8173-disp-rdma5à  ¶f8g9nrdma@1400f000mediatek,mt8173-disp-rdma5ð  ·f8g9nrdma@14010000mediatek,mt8173-disp-rdma5  ¸f8g9‚nwdma@14011000mediatek,mt8173-disp-wdma5  ¹f8g9nwdma@14012000mediatek,mt8173-disp-wdma5   ºf8g9ƒncolor@14013000mediatek,mt8173-disp-color50  »f8color@14014000mediatek,mt8173-disp-color5@  ¼f8aal@14015000mediatek,mt8173-disp-aal5P  ½f8gamma@14016000mediatek,mt8173-disp-gamma5`  ¾f8merge@14017000mediatek,mt8173-disp-merge5pf8split@14018000mediatek,mt8173-disp-split5€f8split@14019000mediatek,mt8173-disp-split5f8ufoe@1401a000mediatek,mt8173-disp-ufoe5   ¿f8dsi@1401b000mediatek,mt8173-dsi5°  Àf8$8%;menginedigitalhsõ;‰dphy ¹disableddsi@1401c000mediatek,mt8173-dsi5À  Áf8&8'<�menginedigitalhs“<�‰dphy ¹disableddpi@1401d000mediatek,mt8173-dpi5Ð  Âf8(8)mpixelenginepll¹okayportendpoint—=Bpwm@1401e0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm5à§f8!8 mmainmm¹okay>defaultL>pwm@1401f0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm5ð§f8#8"mmainmm ¹disabledmutex@14020000mediatek,mt8173-disp-mutex5  ©f8larb@14021000mediatek,mt8173-smi-larb5²?f88mapbsmismi@14022000mediatek,mt8173-smi-common5 f88mapbsmi?od@14023000mediatek,mt8173-disp-od50f8hdmi@14025000mediatek,mt8173-hdmi5P  Î f8,8-8.8/mpixelpllbclkspdif>defaultL@õA‰hdmi¿8 ïsÿA¹okayports+port@05endpoint—B=port@15endpoint—CHlarb@14027000mediatek,mt8173-smi-larb5p²?f8282mapbsmiclock-controller@15000000mediatek,mt8173-imgsyssyscon5EDlarb@15001000mediatek,mt8173-smi-larb5²?fDDmapbsmiclock-controller@16000000mediatek,mt8173-vdecsyssyscon5EEvcodec@16000000mediatek,mt8173-vcodec-decÀ5 0@Phpx„  Ìn@g9 9!9%9&9'9"9#9$|:@f >lWMiNZmvcodecpllunivpll_d2clk_cci400_selvdec_selvdecpllvencpllvenc_lt_selvdec_bus_clk_src(ïilW ÿN>MRXU†€/¯larb@16010000mediatek,mt8173-smi-larb5²?fEEmapbsmiclock-controller@18000000mediatek,mt8173-vencsyssyscon5EFlarb@18001000mediatek,mt8173-smi-larb5²?fFFmapbsmivcodec@18002000mediatek,mt8173-vcodec-enc 5   ÆÊn g9`9a9b9c9d9i9j9k9l9m9n9 9¡9¤9¨9§9¥9¦9¢9£|: fPX?i2mvenc_sel_srcvenc_selvenc_lt_sel_srcvenc_lt_selïXiÿMNclock-controller@19000000!mediatek,mt8173-vencltsyssyscon5EGlarb@19001000mediatek,mt8173-smi-larb5²?fGGmapbsmimemory@40000000)memory5@€chosenconnectorhdmi-connectorÔhdmi0dportendpoint—HCextcon_iddiglinux,extcon-usb-gpio Ú4regulator@0regulator-fixed 5usb_vbusDLK@\LK@ Ý‚â7regulator@1regulator-fixed5vbusDLK@\LK@ Ý â3 compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mdp_rdma0mdp_rdma1mdp_rsz0mdp_rsz1mdp_rsz2mdp_wdma0mdp_wrot0mdp_wrot1serial0serial1serial2serial3opp-sharedphandleopp-hzopp-microvoltcpudevice_typeregenable-methodcpu-idle-states#cooling-cellsclocksclock-namesoperating-points-v2proc-supplysram-supplyentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paraminterruptsinterrupt-affinitycpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionrangesalignmentno-map#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxinput-enablebias-pull-downbias-disableoutput-lowbias-pull-updrive-strength#power-domain-cellsinfracfgreg-namesresetsreset-namespower-domainsregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-enable-ramp-delaystatusmemory-regionmediatek,larbs#iommu-cellsmediatek,ibiasmediatek,ibias_up#phy-cells#mbox-cells#io-channel-cellsclock-divpinctrl-namespinctrl-0regulator-min-microampregulator-max-microampmediatek,pad-select#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namesassigned-clocksassigned-clock-parentspinctrl-1bus-widthmax-frequencycap-mmc-highspeedmediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-cmd-resp-sel-risingvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr25cd-gpiosphysmediatek,syscon-wakeupvusb33-supplyvbus-supplyextcondr_modewakeup-sourcepinctrl-2assigned-clock-ratesiommusmediatek,larbmediatek,vpuphy-namesphyremote-endpoint#pwm-cellsmediatek,smimediatek,syscon-hdmilabelid-gpioenable-active-high