Ð þíN)8J$(Iì$mediatek,mt2712-evbmediatek,mt2712 +!7MediaTek MT2712 evaluation boardopp_table0operating-points-v2=Hopp00P#¤Á€WB@opp01P)׫€WB@opp02P/D8@WB@opp_table1operating-points-v2=H opp00P#¤Á€WB@opp01P)׫€WB@opp02P/D8@WB@opp03P5w"@WB@opp04P;ª @WB@cpus+cpu-mapcluster0core0ecore1ecluster1core0ecpu@0icpuarm,cortex-a35uy%€cpuintermediateŒ˜¬ Hcpu@1icpuarm,cortex-a35u¼psciy%€cpuintermediateŒ˜¬ Hcpu@200icpuarm,cortex-a72u¼psciy'€cpuintermediateŒ ˜ ¬ Hidle-statesÊpscicpu-sleep-0arm,idle-state×èdùP ÐH cluster-sleep-0arm,idle-state×è^ùP ¸H psci arm,psci-0.2Ãsmcdummy26m fixed-clock1Œº€AHdummyclk fixed-clock1Œº€AHoscillator@0 fixed-clockA1Œº€Nclk26mH"oscillator@1 fixed-clockA1€Nclk32koscillator@2 fixed-clockA1úð€Nclkfpcoscillator@3 fixed-clockA1c. Nclkaud_ext_i_0oscillator@4 fixed-clockA1 ¸Nclkaud_ext_i_1oscillator@5 fixed-clockA1 Ä@Nclkaud_ext_i_2oscillator@6 fixed-clockA1ÉÀNclki2si0_mck_ioscillator@7 fixed-clockA1ÉÀNclki2si1_mck_ioscillator@8 fixed-clockA1ÉÀNclki2si2_mck_ioscillator@9 fixed-clockA1ÉÀNclktdmin_mclk_itimerarm,armv8-timer 0a   syscon@10000000 mediatek,mt2712-topckgensysconuAHsyscon@10001000 mediatek,mt2712-infracfgsysconuAHsyscon@10003000mediatek,mt2712-pericfgsysconu0AHsyscfg_pctl_a@10005000%mediatek,mt2712-pctl-a-syscfgsysconuPHpinctrl@10005000mediatek,mt2712-pinctrlu°l“£¯Ä a™H3usb0_iddigH!pins_iddigÕ Üusb1_iddigH)pins_iddigÕÜscpsys@10006000mediatek,mt2712-scpsyssysconéu`0yeihœg€mmmfgvencjpgdecaudiovdecýHserial@1000f000*mediatek,mt2712-uartmediatek,mt6577-uartuð ay €baudbus disabledspi@10013000mediatek,mt2712-spi-slaveu0 ay€spi  disablediommu@10205000mediatek,mt2712-m4uu P a“y€bclk4Csyscon@10209000"mediatek,mt2712-apmixedsyssysconu Aiommu@1020a000mediatek,mt2712-m4uu   a‘y€bclk 4Csyscon@10220000mediatek,mt2712-mcucfgsysconu"AHinterrupt-controller@10220a80.mediatek,mt2712-sysirqmediatek,mt6577-sysirq¯Ä u" €@Hinterrupt-controller@10510000 arm,gic-400Ä ¯@uQRTV a H adc@11001000mediatek,mt2712-auxadcuy€mainPokayserial@11002000*mediatek,mt2712-uartmediatek,mt6577-uartu  a[y €baudbusokayserial@11003000*mediatek,mt2712-uartmediatek,mt6577-uartu0 a\y €baudbus disabledserial@11004000*mediatek,mt2712-uartmediatek,mt6577-uartu@ a]y €baudbus disabledserial@11005000*mediatek,mt2712-uartmediatek,mt6577-uartuP a^y €baudbus disabledpwm@11006000mediatek,mt2712-pwmu`b aMPyf  1€topmainpwm1pwm2pwm3pwm4pwm5pwm6pwm7pwm8 disabledi2c@11007000mediatek,mt2712-i2c up€€ aTmy  €maindma+ disabledi2c@11008000mediatek,mt2712-i2c u€€ aUmy  €maindma+ disabledi2c@11009000mediatek,mt2712-i2c u€€ aVmy  €maindma+ disabledspi@1100a000mediatek,mt2712-spi+u  avyl€parent-clksel-clkspi-clk disablednfi@1100e000mediatek,mt2712-nfcuà a`y½€nfi_clkpad_clkw+ disabledecc@1100f000mediatek,mt2712-eccuð a_y¿ €nfiecc_clk disabledHi2c@11010000mediatek,mt2712-i2c u€ aWmy  €maindma+ disabledi2c@11011000mediatek,mt2712-i2c u€€ aXmy  €maindma+ disabledi2c@11013000mediatek,mt2712-i2c u0€ aZmy  €maindma+ disabledspi@11015000mediatek,mt2712-spi+uP ayl€parent-clksel-clkspi-clk disabledspi@11016000mediatek,mt2712-spi+u` ayl€parent-clksel-clkspi-clk disabledspi@10012000mediatek,mt2712-spi+u  ayl€parent-clksel-clkspi-clk disabledspi@11018000mediatek,mt2712-spi+u€ ayl€parent-clksel-clkspi-clk disabledserial@11019000*mediatek,mt2712-uartmediatek,mt6577-uartu a~y €baudbus disabledmmc@11230000mediatek,mt2712-mmcu# aO y *,&€sourcehclkbus_clksource_cg disabledmmc@11240000mediatek,mt2712-mmcu$ aPy c'€sourcehclksource_cg disabledmmc@11250000mediatek,mt2712-mmcu% aQyc(€sourcehclksource_cg disabledusb@11271000#mediatek,mt2712-mtu3mediatek,mtu3 u'0( ‚macippc azŒ‘yn€sys_ck Ÿ+¶okay½É ÐotgØæûdefault !xhci@11270000'mediatek,mt2712-xhcimediatek,mtk-xhciu'‚mac a{‘ yn"€sys_ckref_ckokay½#usb-phy@11290000mediatek,mt2712-u3phy+¶okayusb-phy@11290000u)y"€refokayHusb-phy@11298000u)€y"€refokayHusb-phy@11298700u)‡ y"€refokayH*usb@112c1000#mediatek,mt2712-mtu3mediatek,mtu3 u,0- ‚macippc aøŒ$%&‘yn€sys_ck Ÿ+¶okay½'É(ÐotgØûdefault )xhci@112c0000'mediatek,mt2712-xhcimediatek,mtk-xhciu,‚mac aù‘ yn"€sys_ckref_ckokayusb-phy@112e0000mediatek,mt2712-u3phy+¶okayusb-phy@112e0000u.y"€refokayH$usb-phy@112e8000u.€y"€refokayH%usb-phy@112e8700u.‡ y"€refokayH&pcie@11700000mediatek,mt2712-pcieipci up/ð ‚port0port1+asu yƒ„#$ €sys_ck0sys_ck1ahb_ck0ahb_ck1Œ*&0pcie-phy0pcie-phy1:ÿ¶‚ pcie@0,0ipci disabledu+ĶD`W++++interrupt-controller¯ÄH+pcie@1,0ipci disabledu+ĶD`W,,,,interrupt-controller¯ÄH,syscon@13000000mediatek,mt2712-mfgcfgsysconuAsyscon@14000000mediatek,mt2712-mmsyssysconuAH.larb@14021000mediatek,mt2712-smi-larbue-r‘y..€apbsmiHsmi@14022000mediatek,mt2712-smi-commonu ‘y..€apbsmiH-larb@14027000mediatek,mt2712-smi-larbupe/r‘y.,.,€apbsmiHlarb@14030000mediatek,mt2712-smi-larbue/r‘y....€apbsmiHsmi@14031000mediatek,mt2712-smi-commonu‘y.-.-€apbsmiH/larb@14032000mediatek,mt2712-smi-larbu e/r‘y.8.8€apbsmiHsyscon@15000000mediatek,mt2712-imgsyssysconuAH0larb@15001000mediatek,mt2712-smi-larbue-r‘y00€apbsmiHsyscon@15010000mediatek,mt2712-bdpsyssysconuAsyscon@16000000mediatek,mt2712-vdecsyssysconuAH1larb@16010000mediatek,mt2712-smi-larbue-r‘y11€apbsmiHsyscon@18000000mediatek,mt2712-vencsyssysconuAH2larb@18001000mediatek,mt2712-smi-larbue-r‘y22€apbsmiHlarb@18002000mediatek,mt2712-smi-larbu e-r‘y22€apbsmiHsyscon@19000000!mediatek,mt2712-jpgdecsyssysconuAaliasesƒ/serial@11002000memory@40000000imemoryu@€chosen‹serial0:921600n8fixedregulator@0regulator-fixed —vproc_buck0¦B@¾B@Hfixedregulator@1regulator-fixed —vproc_buck1¦B@¾B@H extcon_iddiglinux,extcon-usb-gpio Ö3 H extcon_iddig1linux,extcon-usb-gpio Ö3H(regulator@2regulator-fixed—p0_vbus¦LK@¾LK@ Ù3 ÞHregulator@3regulator-fixed—p1_vbus¦LK@¾LK@ Ù3ÞH'regulator@4regulator-fixed—p2_vbus¦LK@¾LK@ Ù3ÞH#regulator@5regulator-fixed—p3_vbus¦LK@¾LK@ Ù3Þñ compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltcpudevice_typeregclocksclock-namesproc-supplyoperating-points-v2cpu-idle-statesenable-methodentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramclock-frequency#clock-cellsclock-output-namesinterruptsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxbias-pull-up#power-domain-cellsinfracfgstatusassigned-clocksassigned-clock-parentsmediatek,larbs#iommu-cells#io-channel-cells#pwm-cellsclock-divecc-enginereg-namesphyspower-domainsmediatek,syscon-wakeuprangesvbus-supplyextcondr_modewakeup-sourcemediatek,u3p-dis-mskpinctrl-namespinctrl-0#phy-cellsenable-manual-drdphy-namesbus-rangeinterrupt-map-maskinterrupt-mapmediatek,smimediatek,larb-idserial0stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltid-gpioenable-active-highregulator-always-on