Ð þí§8(‹älge,lg1313-reflge,lg1313&/7LG Electronics, DTV SoC LG1313 Reference Boardcpuscpu@0=cpuarm,cortex-a53IM^cpu@1=cpuarm,cortex-a53IfpsciM^cpu@2=cpuarm,cortex-a53IfpsciM^cpu@3=cpuarm,cortex-a53IfpsciM^l2-cache0cache^psciarm,psci-0.2arm,pscimsmct„€„ˆ„interrupt-controller@c0001000 arm,gic-400 0IÀÀ À@ À` ^pmuarm,cortex-a53-pmu0µ•–—˜Àtimerarm,armv8-timer0µ   clk_busÓ fixed-clockà Í=€ðBUSCLK^soc simple-bus&ethernet@c3700000 cdns,gem IÃp µ%  hclkpclkrmii&amba2 simple-bus&timer@fd100000 arm,sp804 Iý µ  apb_pclkwatchdog@fd200000arm,sp805arm,primecell Iý  µ  apb_pclkserial@fe000000arm,pl011arm,primecell Iþ µ  apb_pclkDokayserial@fe100000arm,pl011arm,primecell Iþ µ  apb_pclk Ddisabledserial@fe200000arm,pl011arm,primecell Iþ  µ  apb_pclk Ddisabledspi@fe800000arm,pl022arm,primecell Iþ€ µ  apb_pclkspi@fe900000arm,pl022arm,primecell Iþ µ  apb_pclkdma@c1128000arm,pl330arm,primecell IÁ€ µ  apb_pclkgpio@fd400000Karm,pl061arm,primecellW Iý@  apb_pclk Ddisabledgpio@fd410000Karm,pl061arm,primecellW IýA  apb_pclk Ddisabledgpio@fd420000Karm,pl061arm,primecellW IýB  apb_pclk Ddisabledgpio@fd430000Karm,pl061arm,primecellW IýC  apb_pclkgpio@fd440000Karm,pl061arm,primecellW IýD  apb_pclk Ddisabledgpio@fd450000Karm,pl061arm,primecellW IýE  apb_pclk Ddisabledgpio@fd460000Karm,pl061arm,primecellW IýF  apb_pclk Ddisabledgpio@fd470000Karm,pl061arm,primecellW IýG  apb_pclk Ddisabledgpio@fd480000Karm,pl061arm,primecellW IýH  apb_pclk Ddisabledgpio@fd490000Karm,pl061arm,primecellW IýI  apb_pclk Ddisabledgpio@fd4a0000Karm,pl061arm,primecellW IýJ  apb_pclk Ddisabledgpio@fd4b0000Karm,pl061arm,primecellW IýK  apb_pclkgpio@fd4c0000Karm,pl061arm,primecellW IýL  apb_pclk Ddisabledgpio@fd4d0000Karm,pl061arm,primecellW IýM  apb_pclk Ddisabledgpio@fd4e0000Karm,pl061arm,primecellW IýN  apb_pclk Ddisabledgpio@fd4f0000Karm,pl061arm,primecellW IýO  apb_pclk Ddisabledgpio@fd500000Karm,pl061arm,primecellW IýP  apb_pclk Ddisabledgpio@fd510000Karm,pl061arm,primecellW IýQ  apb_pclkaliasesg/amba/serial@fe000000o/amba/serial@fe100000w/amba/serial@fe200000memory=memory I chosenserial0:115200n8 #address-cells#size-cellscompatibleinterrupt-parentmodeldevice_typeregnext-level-cachephandleenable-methodcpu_suspendcpu_offcpu_on#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinity#clock-cellsclock-frequencyclock-output-namesrangesclocksclock-namesphy-modemac-address#interrupts-cellsstatus#gpio-cellsgpio-controllerserial0serial1serial2stdout-path