Ð þí_Í8Z0(Yø ARM Juno development board (r2)"arm,juno-r2arm,junoarm,vexpress"1refclk7372800hz fixed-clock=Jp€ Zjuno:uartclkm8clk48mhz fixed-clock=JÜl Zclk48mhzm<�clk50mhz fixed-clock=Júð€Zsmc_clkm refclk100mhz fixed-clock=Jõá Zapb_pclkm refclk400mhz fixed-clock=Jׄ Zfaxi_clkm2smb@8000000 simple-bus"1xu | Ô DEF ¡¢£¤¥ ¦ § ¨ ©clk24mhz fixed-clock=Jn6Zjuno_mb:clk24mhzmclk25mhz fixed-clock=J}x@Zjuno_mb:clk25mhzmrefclk1mhz fixed-clock=JB@Zjuno_mb:refclk1mhzmrefclk32khz fixed-clock=J€Zjuno_mb:refclk32khzmmotherboardarm,vexpress,v2p-p1simple-bus"1|u V2M-Juno®R¶Èrs1mcc-sb-3v3regulator-fixed ÛMCC_SB_3V3ê2Z 2Z mgpio-keys gpio-keyspower-button.2@NtYPOWER _home-button.2@NfYHOME _rlock-button.2@N˜YRLOCK _vol-up-button.2@NsYVOL+ _vol-down-button.2@NrYVOL- _nmi-button.2@NcYNMI _flash@0,00000000arm,vexpress-flashcfi-flash ei tdisabledpartitionsarm,arm-firmware-suiteethernet@2,00000000smsc,lan9118smsc,lan9115 e{†miiœ±ÄËÙiofpga@3,00000000 simple-bus"1u sysctl@20000arm,sp810arm,primecelle Äérefclktimclkapb_pclk=0Ztimerclken0timerclken1timerclken2timerclken3 õmapbregs@10000sysconsimple-mfdeled0register-bit-led› Yvexpress:0 #heartbeat9onled1register-bit-led› Yvexpress:1#mmc09offled2register-bit-led› Yvexpress:2#cpu09offled3register-bit-led› Yvexpress:3#cpu19offled4register-bit-led› Yvexpress:4#cpu29offled5register-bit-led›  Yvexpress:5#cpu39offled6register-bit-led›@ Yvexpress:69offled7register-bit-led›€ Yvexpress:79offmmci@50000arm,pl180arm,primecelle{G·UÄ émclkapb_pclkkmi@60000arm,pl050arm,primecelle{Ä éKMIREFCLKapb_pclkkmi@70000arm,pl050arm,primecelle{Ä éKMIREFCLKapb_pclkwdt@f0000arm,sp805arm,primecelle{Ä éwdogclkapb_pclktimer@110000arm,sp804arm,primecelle{ Äétimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecelle{ Äétimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecelle{Ä  éapb_pclkgpio@1d0000arm,pl061arm,primecelle{Ä  éapb_pclkaq}|mtimer@2a810000arm,armv7-timer-meme*Júð€"1utokayframe@2a830000’ {<�e*ƒmhu@2b1f0000arm,mhuarm,primecelle+{$#Ÿmhu_lpri_rxmhu_hpri_rx¯Ä  éapb_pclkm.iommu@2b500000arm,mmu-401arm,smmu-v1e+P{((»ÈÛ tdisabledm-iommu@2b600000arm,mmu-401arm,smmu-v1e+`{**»ÈÛè minterrupt-controller@2c010000arm,gic-400arm,cortex-a15-gic@e,,ð ,ð ,ð "|1} { ?u,mv2m@0arm,gic-v2m-frameöem,v2m@10000arm,gic-v2m-frameöev2m@20000arm,gic-v2m-frameöev2m@30000arm,gic-v2m-frameöetimerarm,armv8-timer0{ ?? ? ?etf@20010000 arm,coresight-tmcarm,primecelle Ä  éapb_pclkè in-portsportendpoint mout-portsportendpoint mBtpiu@20030000!arm,coresight-tpiuarm,primecelle Ä  éapb_pclkè in-portsportendpointmfunnel@20040000+arm,coresight-dynamic-funnelarm,primecelle Ä  éapb_pclkè out-portsportendpointm in-ports"1port@0eendpointmport@1eendpointm!etr@20070000 arm,coresight-tmcarm,primecelle Ä  éapb_pclkè in-portsportendpointmstm@20100000 arm,coresight-stmarm,primecell e (/stm-basestm-stimulus-baseÄ  éapb_pclkè out-portsportendpointm>replicator@20120000/arm,coresight-dynamic-replicatorarm,primecelle Ä  éapb_pclkè out-ports"1port@0eendpointmport@1eendpointmin-portsportendpointmAcpu-debug@22010000&arm,coresight-cpu-debugarm,primecelle"Ä  éapb_pclkè 9etm@22040000"arm,coresight-etm4xarm,primecelle"Ä  éapb_pclkè 9out-portsportendpointmfunnel@220c0000+arm,coresight-dynamic-funnelarm,primecelle" Ä  éapb_pclkè out-portsportendpointmin-ports"1port@0eendpointmport@1eendpointmcpu-debug@22110000&arm,coresight-cpu-debugarm,primecelle"Ä  éapb_pclkè 9etm@22140000"arm,coresight-etm4xarm,primecelle"Ä  éapb_pclkè 9out-portsportendpointmcpu-debug@23010000&arm,coresight-cpu-debugarm,primecelle#Ä  éapb_pclkè 9etm@23040000"arm,coresight-etm4xarm,primecelle#Ä  éapb_pclkè 9out-portsportendpoint m"funnel@230c0000+arm,coresight-dynamic-funnelarm,primecelle# Ä  éapb_pclkè out-portsportendpoint!min-ports"1port@0eendpoint"m port@1eendpoint#m'port@2eendpoint$m)port@3eendpoint%m+cpu-debug@23110000&arm,coresight-cpu-debugarm,primecelle#Ä  éapb_pclkè 9&etm@23140000"arm,coresight-etm4xarm,primecelle#Ä  éapb_pclkè 9&out-portsportendpoint'm#cpu-debug@23210000&arm,coresight-cpu-debugarm,primecelle#!Ä  éapb_pclkè 9(etm@23240000"arm,coresight-etm4xarm,primecelle#$Ä  éapb_pclkè 9(out-portsportendpoint)m$cpu-debug@23310000&arm,coresight-cpu-debugarm,primecelle#1Ä  éapb_pclkè 9*etm@23340000"arm,coresight-etm4xarm,primecelle#4Ä  éapb_pclkè 9*out-portsportendpoint+m%sram@2e000000arm,juno-sram-nsmmio-srame.€"1u.€scp-shmem@0arm,juno-scp-shmemescp-shmem@200arm,juno-scp-shmemem/pcie@40000000<�arm,juno-r1-pcieplda,xpressrich3-axipci-host-ecam-generic=pcie@IÿS"1ÛTu_€€PPB@@|  ˆ‰Š‹d,tokayo~-scpi arm,scpiˆ./clocksarm,scpi-clocksscpi-dvfsarm,scpi-dvfs-clocks= •ZatlclkaplclkgpuclkmEscpi-clkarm,scpi-variable-clocks=•Zpxlclkm4scpi-power-domainsarm,scpi-power-domains£¯m sensorsarm,scpi-sensorsÃm0thermal-zonespmicÙèçdý0socÙèçdý0big-clusterÙèçdý0tokaylittle-clusterÙèçdý0tokaygpu0Ùèçdý0tokaygpu1Ùèçdý0tokayiommu@7fb00000arm,mmu-401arm,smmu-v1e°{__»ÈÛ tdisabledm1iommu@7fb10000arm,mmu-401arm,smmu-v1e±{cc»Èm3iommu@7fb20000arm,mmu-401arm,smmu-v1e²{aa»Èm6iommu@7fb30000arm,mmu-401arm,smmu-v1e³{ee»ÈÛm;dma@7ff00000arm,pl330arm,primecelleð & l{XYZ[\lmnoH111111111Ä2 éapb_pclkhdlcd@7ff50000 arm,hdlcdeõ {]3Ä4épxlclkportendpoint5m:hdlcd@7ff60000 arm,hdlcdeö {U6Ä4épxlclkportendpoint7m9uart@7ff80000arm,pl011arm,primecelleø {SÄ8 éuartclkapb_pclki2c@7ffa0000snps,designware-i2ceú"1 {hJ€4ôÄ hdmi-transmitter@70 nxp,tda998xepportendpoint9m7hdmi-transmitter@71 nxp,tda998xeqportendpoint:m5ohci@7ffb0000 generic-ohcieû {t;Ä<�ehci@7ffc0000 generic-ehcieü {u;Ä<�memory-controller@7ffd0000arm,pl354arm,primecelleý{VWÄ  éapb_pclkmemory@80000000=memory e€€€tlx@60000000 simple-bus"1u`|  ¨funnel@20130000+arm,coresight-dynamic-funnelarm,primecelle Ä  éapb_pclkè out-portsportendpoint=m?in-portsportendpoint>metf@20140000 arm,coresight-tmcarm,primecelle Ä  éapb_pclkè in-portsportendpoint?m=out-portsportendpoint@mCfunnel@20150000+arm,coresight-dynamic-funnelarm,primecelle Ä  éapb_pclkè out-portsportendpointAmin-ports"1port@0eendpointIBm port@1eendpointICm@aliasesT/uart@7ff80000chosen\serial0:115200n8psci arm,psci-0.2hsmccpus"1cpu-mapcluster0core09core19cluster1core09core19&core29(core39*idle-statesopscicpu-sleep-0arm,idle-state|“¤,µ°ÅÐmFcluster-sleep-0arm,idle-state|“¤µ°Å ÄmGcpu@0arm,cortex-a72e=cpuÖpsciäÀñ@€@/<�DÄEMFG]pÂmcpu@1arm,cortex-a72e=cpuÖpsciäÀñ@€@/<�DÄEMFG]pÂmcpu@100arm,cortex-a53e=cpuÖpsciä€ñ@€@/€<�HÄEMFG]åpŒmcpu@101arm,cortex-a53e=cpuÖpsciä€ñ@€@/€<�HÄEMFG]åpŒm&cpu@102arm,cortex-a53e=cpuÖpsciä€ñ@€@/€<�HÄEMFG]åpŒm(cpu@103arm,cortex-a53e=cpuÖpsciä€ñ@€@/€<�HÄEMFG]åpŒm*l2-cache0cacheæ ó@mDl2-cache1cacheæó@mHpmu-a72arm,cortex-a72-pmu{Špmu-a53arm,cortex-a53-pmu0{Š&(* modelcompatibleinterrupt-parent#address-cells#size-cells#clock-cellsclock-frequencyclock-output-namesphandleranges#interrupt-cellsinterrupt-map-maskinterrupt-maparm,hbiarm,vexpress,sitearm,v2m-memory-mapregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ondebounce-intervalwakeup-sourcelinux,codelabelgpiosregbank-widthstatusinterruptsphy-modereg-io-widthsmsc,irq-active-highsmsc,irq-push-pullclocksvdd33a-supplyvddvario-supplyclock-namesassigned-clocksassigned-clock-parentsoffsetlinux,default-triggerdefault-statemax-frequencyvmmc-supplygpio-controller#gpio-cellsinterrupt-controllerframe-numberinterrupt-names#mbox-cells#iommu-cells#global-interruptsdma-coherentpower-domainsmsi-controllerremote-endpointiommusarm,scatter-gatherreg-namescpudevice_typebus-rangelinux,pci-domainmsi-parentiommu-map-maskiommu-mapmboxesshmemclock-indicesnum-domains#power-domain-cells#thermal-sensor-cellspolling-delaypolling-delay-passivethermal-sensors#dma-cells#dma-channels#dma-requestsi2c-sda-hold-time-nsslave-modeserial0stdout-pathmethodentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-idle-statescapacity-dmips-mhzdynamic-power-coefficientinterrupt-affinity