Ð þí7„83 (x2Ô3hisilicon,hi3798cv200-poplarhisilicon,hi3798cv200 +#7HiSilicon Poplar Development Boardpsci arm,psci-0.2=smccpus+cpu@0arm,cortex-a53DcpuPTpscicpu@1arm,cortex-a53DcpuPTpscicpu@2arm,cortex-a53DcpuPTpscicpu@3arm,cortex-a53DcpuPTpsciinterrupt-controller@f1001000 arm,gic-400 Pññ bsˆtimerarm,armv8-timer0   soc@f0000000 simple-bus+›ðclock-reset-controller@8a22000,hisilicon,hi3798cv200-crgsysconsimple-mfdP¢ ¢¯ˆreset-controllerti,syscon-reset¯8¼Ì Ì Ì Ì ˆ system-controller@8000000%hisilicon,hi3798cv200-sysctrlsysconP¢¯ˆperipheral-controller@8a200001hisilicon,hi3798cv200-perictrlsysconsimple-mfdP¢+ ›¢usb2-phy@120hisilicon,hi3798cv200-usb2-phyP Ê( Ѽ+phy@0PØ Ñ¼ˆphy@1PØ Ñ¼ usb2-phy@124hisilicon,hi3798cv200-usb2-phyP$Ê) Ѽ+phy@0PØ Ñ¼ phy@850hisilicon,hi3798cv200-combphyPPØÊ* шã*óõáphy@858hisilicon,hi3798cv200-combphyPXØÊ! ш ã!óõá  ˆ pinconf@8a21000pinconf-singleP¢€8 V°s  VW"%&).6@GHNOPFXˆ gpio-rangeˆemmc-pins-1H® $ ßú°ðˆemmc-pins-2®( ßúðˆemmc-pins-3®, ßú00ˆemmc-pins-4®0 ßú00ˆ serial@8b00000arm,pl011arm,primecellP° 1Ê 1apb_pclk=okayserial@8b02000arm,pl011arm,primecellP°  3Ê 1apb_pclk=okay DLS-UART0i2c@8b10000hisilicon,hix5hd2-i2cP±+ &J€Ê=okayDLS-I2C0i2c@8b11000hisilicon,hix5hd2-i2cP±+ 'J€Ê =disabledi2c@8b12000hisilicon,hix5hd2-i2cP± + (J€Ê=okayDLS-I2C1i2c@8b13000hisilicon,hix5hd2-i2cP±0+ )J€Ê  =disabledi2c@8b14000hisilicon,hix5hd2-i2cP±@+ *J€Ê  =disabledspi@8b1a000arm,pl022arm,primecellP±  -Z aÊ  1apb_pclk+=okayDLS-SPI0mmc@9820000 snps,dw-mshcP ‚ "Ê1ciubiu Ñœjreset=okayv€mmc@9830000hisilicon,hi3798cv200-dw-mshcP ƒ # Ê1ciubiuciu-sampleciu-drive Ñ jreset=okay‘defaultŸ ©J ë´ÆÓâvgpio@8b20000arm,pl061arm,primecellP² lðsb Ê 1apb_pclk =disabledgpio@8b21000arm,pl061arm,primecellP² mðsbP       Ê 1apb_pclk=okayGPIO-EGPIO-FGPIO-Jgpio@8b22000arm,pl061arm,primecellP²  nðsb   Ê 1apb_pclk=okay&GPIO-HGPIO-IGPIO-LGPIO-GGPIO-Kgpio@8b23000arm,pl061arm,primecellP²0 oðsb@   V WÊ 1apb_pclk=okayGPIO-CGPIO-Bgpio@8b24000arm,pl061arm,primecellP²@ pðsb0  " %Ê 1apb_pclk=okayGPIO-Dˆgpio@8004000arm,pl061arm,primecellP@ qðsbÊ 1apb_pclk=okay"USER-LED-1USER-LED-2GPIO-Aˆgpio@8b26000arm,pl061arm,primecellP²` rðsb  & )Ê 1apb_pclk=okayUSER-LED-0ˆgpio@8b27000arm,pl061arm,primecellP²p sðsb .Ê 1apb_pclk =disabledˆgpio@8b28000arm,pl061arm,primecellP²€ tðsb 6Ê 1apb_pclk =disabledgpio@8b29000arm,pl061arm,primecellP² uðsb @ GÊ 1apb_pclk =disabledgpio@8b2a000arm,pl061arm,primecellP²  vðsb0 H N OÊ 1apb_pclk=okayUSER-LED-3ˆgpio@8b2b000arm,pl061arm,primecellP²° wðsb  P FÊ 1apb_pclk =disabledgpio@8b2c000arm,pl061arm,primecellP²À xðsb XÊ 1apb_pclk =disabledethernet@98400002hisilicon,hi3798cv200-gmachisilicon,hisi-gmac-v2P „ „0  GÊ1mac_coremac_ifc ÑÌÌ jmac_coremac_ifcphy =disabledethernet@98410002hisilicon,hi3798cv200-gmachisilicon,hisi-gmac-v2P „ „0 HÊ 1mac_coremac_ifc ÑÌ Ì jmac_coremac_ifcphy=okay+( 3rgmii <�''u0phy@3Pˆ ir@8001000hisilicon,hix5hd2-irP /Ê=okaypcie@9860000hisilicon,hi3798cv200-pcieP † Zcontrolrc-dbiconfig+Dpcidn0›ð‚𠐀xmsibˆ ›ƒ Ê1auxpipesysbus$ÑŒŒŒ jsoftsysbus© ®phy=okay ¸Äohci@9880000 generic-ohciP ˆ CÊ"%&1busclk12clk48 Ѹ jbus©®usb=okayehci@9890000 generic-ehciP ‰ BÊ"#$ 1busphyutmi$Ѹ ¸¸  jbusphyutmi©®usb=okayaliasesÑ/soc@f0000000/serial@8b00000Ù/soc@f0000000/serial@8b02000chosenáserial0:115200n8memory@0DmemoryP€leds gpio-ledsuser-led0 Dgreen:user1 d íheartbeatoffuser-led1 Dgreen:user2 dímmc0offuser-led2 Dgreen:user3 dímmc1offuser-led3 Dgreen:user4 dínoneoffregulator-pcieregulator-fixed !3V3_PCIE002Z H2Z  `eˆ compatibleinterrupt-parent#address-cells#size-cellsmodelmethoddevice_typeregenable-method#interrupt-cellsinterrupt-controllerphandleinterruptsranges#clock-cells#reset-cellsti,reset-bitsclocksresets#phy-cellsassigned-clocksassigned-clock-rateshisilicon,fixed-modehisilicon,mode-select-bitspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,slew-ratepinctrl-single,drive-strengthclock-namesstatuslabelclock-frequencynum-cscs-gpiosreset-namesbus-widthcap-sd-highspeedpinctrl-namespinctrl-0fifo-depthcap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vnon-removablegpio-controller#gpio-cellsgpio-rangesgpio-line-namesphy-handlephy-modehisilicon,phy-reset-delays-usreg-namesbus-rangenum-lanesinterrupt-namesinterrupt-map-maskinterrupt-mapphysphy-namesreset-gpiosvpcie-supplyserial0serial2stdout-pathlinux,default-triggerdefault-statepanic-indicatorregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-high