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þíOò8KÀ(2Kˆ+hisilicon,hi3670-hikey970hisilicon,hi3670+ 7HiKey970psci
arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53HcpuTXpscifcpu@1arm,cortex-a53HcpuTXpscifcpu@2arm,cortex-a53HcpuTXpscifcpu@3arm,cortex-a53HcpuTXpscifcpu@100arm,cortex-a73HcpuTXpscifcpu@101arm,cortex-a73HcpuTXpscifcpu@102arm,cortex-a73HcpuTXpscifcpu@103arm,cortex-a73HcpuTXpscif interrupt-controller@e82b0000arm,gic-400@Tè+è+ è+@ è+` n ÿŠftimerarm,armv8-timer0
ÿÿÿ
ÿŸLsocsimple-bus+¯crg_ctrl@fff35000 hisilicon,hi3670-crgctrlsysconTÿóP¶f
crg_rst_controller.hisilicon,hi3670-resethisilicon,hi3660-resetÃÐ
fpctrl@e8a09000hisilicon,hi3670-pctrlsysconTè ¶crg_ctrl@fff34000 hisilicon,hi3670-pmuctrlsysconTÿó@¶sctrl@fff0a000hisilicon,hi3670-sctrlsysconTÿð ¶fiomcu@ffd7e000hisilicon,hi3670-iomcusysconTÿ×à¶media1_crgctrl@e87ff000#hisilicon,hi3670-media1-crgsysconTèð¶media2_crgctrl@e8900000#hisilicon,hi3670-media2-crgsysconTè¶serial@fdf02000arm,pl011arm,primecellTýð Jà
²
çuartclkapb_pclkódefaultokay HS-UART0serial@fdf00000arm,pl011arm,primecellTýðKà
ª
çuartclkapb_pclkódefault disabledserial@fdf03000arm,pl011arm,primecellTýð0Là
®
çuartclkapb_pclkódefault
okay LS-UART0serial@ffd74000arm,pl011arm,primecellTÿ×@rà
çuartclkapb_pclkódefault disabledserial@fdf01000arm,pl011arm,primecellTýðMà
«
çuartclkapb_pclkódefault disabledserial@fdf05000arm,pl011arm,primecellTýðPNà
¯
çuartclkapb_pclkódefault disabledserial@fff32000arm,pl011arm,primecellTÿó Oà
çuartclkapb_pclkódefaultokay LS-UART1gpio@e8a0b000arm,pl061arm,primecellTè °T( 4Šnà
} çapb_pclkK@TP901GPIO_003_USB_HUB_RESET_NNC[AP_GPS_REF_CLK][I2C3_SCL][I2C3_SDA]gpio@e8a0c000arm,pl061arm,primecellTè ÀU(Šnà
~ çapb_pclk[@[UART0_CTS][UART0_RTS][UART0_TXD][UART0_RXD][USER_LED5]GPIO-I[USER_LED3][USER_LED4]gpio@e8a0d000arm,pl061arm,primecellTè ÐV(4Šnà
çapb_pclk^@GPIO-G[CSI0_MCLK][CSI1_MCLK]GPIO_019_BT_ACTIVE[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]gpio@e8a0e000arm,pl061arm,primecellTè àW( 4
Šnà
€ çapb_pclk[@GPIO_024_WIFI_ACTIVEGPIO_025_PERST_M.2[I2C4_SCL][I2C4_SDA]NCGPIO-H[USER_LED1]GPIO-Lgpio@e8a0f000arm,pl061arm,primecellTè ðX(4Šnà
çapb_pclkm@GPIO-KGPIO_033_PMU1_ENGPIO_034_USBSW_SEL[SD_DAT1][SD_DAT2][UART1_RXD][UART1_TXD][SOC_GPS_UART3_CTS_N]gpio@e8a10000arm,pl061arm,primecellTè¡Y(4Šnà
‚ çapb_pclk‘@[SOC_GPS_UART3_RTS_N][SOC_GPS_UART3_RXD][SOC_GPS_UART3_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD][SOC_BT_UART4_TXD]NCgpio@e8a11000arm,pl061arm,primecellTè¡Z(4"Šnà
ƒ çapb_pclkd@NCGPIO_049_USER_LED6GPIO_050_CAN_RSTGPIO_051_WIFI_ENGPIO-DGPIO-JGPIO_054_BT_EN[GPIO_055_SEL]f'gpio@e8a12000arm,pl061arm,primecellTè¡ [(4)Šnà
„ çapb_pclk$@[PCIE_PERST_L]NCNCNCNCNCNCNCgpio@e8a13000arm,pl061arm,primecellTè¡0\(41Šnà
… çapb_pclk@NCNCNCNCNCNCNCNCgpio@e8a14000arm,pl061arm,primecellTè¡@](49Šnà
† çapb_pclk@NCNCNCNCNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTè¡P^(4AŠnà
‡ çapb_pclk@NCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellTè¡`_(4IŠnà
ˆ çapb_pclk@NCNCNCNCNCNCNCNCgpio@e8a17000arm,pl061arm,primecellTè¡p`(4QŠnà
‰ çapb_pclk
@NCgpio@e8a18000arm,pl061arm,primecellTè¡€a(Šnà
Š çapb_pclk@gpio@e8a19000arm,pl061arm,primecellTè¡b(Šnà
‹ çapb_pclk@gpio@e8a1a000arm,pl061arm,primecellTè¡ c(Šnà
Œ çapb_pclk@gpio@e8a1b000arm,pl061arm,primecellTè¡°d(4Šnà
çapb_pclkm@[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3][ETH_ISOLATE]NCgpio@e8a1c000arm,pl061arm,primecellTè¡Àe(4Šnà
Ž çapb_pclk@[MINI1CLK_EN]NCgpio@fff28000arm,pl061arm,primecellTÿò€f(4*Šnà çapb_pclkn@[SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS][POWER_INT_N][CDMA_GPS_SYNC]GPIO_150_PEX_INTAGPIO_151_CAN_INTgpio@fff29000arm,pl061arm,primecellTÿòg(4=Šnà çapb_pclk@gpio@e8a1f000arm,pl061arm,primecellTè¡ðh(4Šnà
çapb_pclkd@[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]GPIO_166_ETHCLK_ENGPIO_167_USER_LED2gpio@e8a20000arm,pl061arm,primecellTè¢i(4Šnà
çapb_pclk*@GPIO_168_GPS_ENGPIO-CGPIO-EGPIO-Bgpio@fff0b000arm,pl061arm,primecellTÿð°j(4Šnà çapb_pclkg@[PMU_PWR_HOLD]GPIO_177_WL_WAKEUP_AP[JTAG_TCK][JTAG_TMS][JTAG_TDI][JTAG_TMS]GPIO_182_FATAL_ERRNCf%gpio@fff0c000arm,pl061arm,primecellTÿðÀk(4Šnà çapb_pclkm@GPIO_184_JTAG_SELGPIO-F[I2C0_SCL][I2C0_SDA][GPIO_188_I2C1_SCL][GPIO_189_I2C1_SDA][I2C1_SCL][I2C2_SDA]gpio@fff0d000arm,pl061arm,primecellTÿðÐl(4Šnà çapb_pclk<�@[SD_LED]NC[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][I2S2_DO]gpio@fff0e000arm,pl061arm,primecellTÿðàm(4Šnà çapb_pclk‹@[I2S2_XCLK][I2S2_XFS]GPIO_202_PERST_ETHGPIO_203_PWRON_DETGPIO_204_PMU1_IRQ_NGPIO_205_SD_DETGPIO_206_GPS_MOTION_INTGPIO_207_HDMI_SELfgpio@fff0f000arm,pl061arm,primecellTÿððn(4Šnà çapb_pclkG@GPIO-AGPIO_209_VBUS_TYPECNCNCNC[SPI0_SCLK][SPI0_DIN][SPI0_DOUT]gpio@fff10000arm,pl061arm,primecellTÿño(4Šnà çapb_pclk|@[SPI0_CS]GPIO_217_HDMI_PDGPIO_218_GPS_WAKEUP_APGPIO_219_M.2CLK_ENGPIO_220_PERST_MINIGPIO_221_CC_INT[PCIE_CLKREQ_L]NCgpio@fff1d000arm,pl061arm,primecellTÿñÐ(4#Šnà çapb_pclki@[PMU0_INT][SPMI_DATA][SPMI_CLK][CAN_SPI_CLK][CAN_SPI_DI][CAN_SPI_DO][CAN_SPI_CS]GPIO_231_HDMI_INTufs@ff3c0000#hisilicon,hi3670-ufsjedec,ufs-2.1 Tÿ<�ÿ>à
çref_clkphy_clkP^„erstdwmmc1@ff37f0002hisilicon,hi3670-dw-mshchisilicon,hi3660-dw-mshcTÿ7ð+‹à
Ÿ
çciubiuŸ0Ô^”eresetqÈokayŸ©¶ÃÐÞïúódefault dwmmc2@fc1830002hisilicon,hi3670-dw-mshchisilicon,hi3660-dw-mshcTü0+Œà
¡
•çciubiuŸ0Ô^”eresetÈokŸ(6@ódefault!"#$wlcore@2
ti,wl1837T%gpio-rangeSf&pinmux@e896c000pinctrl-singleTè–À,tƒ• ³Ð&Rfuart0_pmx_funcêTXfuart2_pmx_func êf
uart3_pmx_func êdhlpfuart4_pmx_func êtx|€fuart6_pmx_funcê\`fpinmux@e896c800pinconf-singleTè–È,t• uart0_cfg_funcêX\þ6ðfuart2_cfg_func êþ6ðfuart3_cfg_func êhlptþ6ðfuart4_cfg_func êx|€„þ6ðfuart6_cfg_funcê`dþ6ðfpinmux@fc182000pinctrl-singleTü (ƒt• ³Ð&
fsdio_pmx_func0êf!pinmux@fc182800pinconf-singleTü((t• sdio_clk_cfg_funcêþ6ððf"sdio_cfg_func(êþ6€ðf#pinmux@ff37e000pinctrl-singleTÿ7à0ƒt• ³Ð&fsd_pmx_func0êfpinmux@ff37e800pinconf-singleTÿ7è0t• sd_clk_cfg_funcêþ6ððfsd_cfg_func(êþ6€ðfpinmux@fff11000pinctrl-singleTÿñ<�ƒt• ³Ð&.fpinmux@fff11800pinconf-singleTÿñ<�t• aliasesT/soc/dwmmc1@ff37f000Z/soc/dwmmc2@fc183000`/soc/serial@fdf02000h/soc/serial@fdf00000p/soc/serial@fdf03000x/soc/serial@ffd74000€/soc/serial@fdf01000ˆ/soc/serial@fdf05000/soc/serial@fff32000chosen˜serial6:115200n8memory@0HmemoryTregulator-1v8regulator-fixed¤fixed-1.8V³w@Ëw@ãf regulator-3v3regulator-fixed¤fixed-3.3V³2Z Ë2Z ÷ãfwlan-en-1-8vregulator-fixed¤wlan-en-regulator³w@Ëw@ 'pf$ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodphandle#interrupt-cellsinterruptsinterrupt-controllerclock-frequencyranges#clock-cells#reset-cellshisi,rst-sysconclocksclock-namespinctrl-namespinctrl-0statuslabelgpio-controller#gpio-cellsgpio-rangesgpio-line-namesfreq-table-hzresetsreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104cap-sd-highspeeddisable-wpcd-invertedcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-ongpiostartup-delay-usenable-active-high