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ÿsocsimple-bus+Âcrg_ctrl@fff35000 hisilicon,hi3660-crgctrlsysconTÿóPÉÞcrg_rst_controllerhisilicon,hi3660-resetÖãÞpctrl@e8a09000hisilicon,hi3660-pctrlsysconTè Écrg_ctrl@fff34000 hisilicon,hi3660-pmuctrlsysconTÿó@Ésctrl@fff0a000hisilicon,hi3660-sctrlsysconTÿð ÉÞ5iomcu@ffd7e000hisilicon,hi3660-iomcusysconTÿ×àÉÞresethisilicon,hi3660-resetãÖÞmailbox@e896b000hisilicon,hi3660-mboxTè–°¤ÀÁóÞstub_clock@e896b500hisilicon,hi3660-stub-clkTè–µÉÿ
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timer@fff14000arm,sp804arm,primecellTÿñ@¤01štimer1timer2apb_pclki2c@ffd71000snps,designware-i2cTÿפv+€š" )default7AokayHLS-I2C0i2c@ffd72000snps,designware-i2cTÿ× ¤w+€š" )default7Aokayadv7533@39Aokadi,adv7533T9i2c@fdf0c000snps,designware-i2cTýðÀ¤Q+€š7"x)default7 Adisabledi2c@fdf0b000snps,designware-i2cTýð°¤:+€š6"`)default7AokayHLS-I2C1serial@fdf02000arm,pl011arm,primecellTýð ¤Jšhuartclkapb_pclk)default7 ! Adisabledserial@fdf00000arm,pl011arm,primecellTýð¤KNrxtxX""š99uartclkapb_pclk)default7#$ Adisabledserial@fdf03000arm,pl011arm,primecellTýð0¤LNrxtxX""š:uartclkapb_pclk)default7%& Adisabledserial@ffd74000arm,pl011arm,primecellTÿ×@¤ršuartclkapb_pclk)default7'(Aokay HLS-UART0serial@fdf01000arm,pl011arm,primecellTýð¤MNrxtxX""š;;uartclkapb_pclk)default7)*Aokaybluetooth
ti,wl1837-st]+j-ÆÀserial@fdf05000arm,pl011arm,primecellTýðP¤NNrxtxX"" š<�<�uartclkapb_pclk)default7,- Adisabledserial@fff32000arm,pl011arm,primecellTÿó ¤Oš
uartclkapb_pclk)default7./Aokay HLS-UART1dma@fdf30000hisilicon,k3-dma-1.0TýótŒ ™ÿþ¤š>ªµhi3660_dmaÞ"dma-controller@e804b000hisilicon,hisi-pcm-asp-dma-1.0Tè°tŒ ¤Ø¾asp_dma_irqrtc@fff04000arm,pl031arm,primecellTÿð@¤.š apb_pclkgpio@e8a0b000arm,pl061arm,primecellTè °¤TÎÞê0~š apb_pclkLöTP901[PMU0_SSI][PMU1_SSI][PMU2_SSI][PMU0_CLKOUT][JTAG_TCK][JTAG_TMS]gpio@e8a0c000arm,pl061arm,primecellTè À¤UÎÞê0~š apb_pclkCö[JTAG_TRST_N][JTAG_TDI][JTAG_TDO]NCNC[I2C3_SCL][I2C3_SDA]NCgpio@e8a0d000arm,pl061arm,primecellTè ФVÎÞê0~š! apb_pclkGöNCNCNCGPIO-JGPIO_020_HDMI_SELGPIO-LGPIO_022_UFSBUCK_INT_NGPIO-Ggpio@e8a0e000arm,pl061arm,primecellTè à¤WÎÞê0~š" apb_pclkJö[CSI0_MCLK][CSI1_MCLK]NC[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]NCgpio@e8a0f000arm,pl061arm,primecellTè ð¤XÎÞê0~š# apb_pclkAöNCNCPWR_BTN_NGPIO_035_PMU2_ENGPIO_036_USB_HUB_RESETNCNCNCÞmgpio@e8a10000arm,pl061arm,primecellT衤YÎÞê0&~š$ apb_pclkQöGPIO-HGPIO_041_HDMI_PDTP904TP905NCNCGPIO_046_HUB_VDD33_ENGPIO_047_PMU1_ENgpio@e8a11000arm,pl061arm,primecellT衤ZÎÞê0.~š% apb_pclkAöNCNCNCGPIO_051_WIFI_ENGPIO-I[SD_DAT1][SD_DAT2][UART1_RXD]Þogpio@e8a12000arm,pl061arm,primecellTè¡ ¤[ÎÞê06~š& apb_pclkyö[UART1_TXD][UART0_CTS][UART0_RTS][UART0_RXD][UART0_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD]gpio@e8a13000arm,pl061arm,primecellTè¡0¤\ÎÞê0>~š' apb_pclk?ö[SOC_BT_UART4_TXD]NC[PMU_HKADC_SSI]NCGPIO_068_SELNCNCNCgpio@e8a14000arm,pl061arm,primecellTè¡@¤]ÎÞê0F~š( apb_pclköNCNCNCGPIO-KNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTè¡P¤^ÎÞê0N~š) apb_pclköNCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellTè¡`¤_ÎÞê0V~š* apb_pclk$öNC[PCIE_PERST_N]NCNCNCNCNCNCÞ:gpio@e8a17000arm,pl061arm,primecellTè¡p¤`ÎÞ ê0^0e~š+ apb_pclköNCNCNCNCgpio@e8a18000arm,pl061arm,primecellTè¡€¤aÎÞê0f~š, apb_pclköNCNCNCNCNCNCNCNCgpio@e8a19000arm,pl061arm,primecellT衤bÎÞê0n~š- apb_pclköNCNCNCNCNCNCNCNCgpio@e8a1a000arm,pl061arm,primecellTè¡ ¤cÎÞê0v~š. apb_pclk'öNCNCNCNCNCNCGPIO_126_BT_ENTP902Þ+gpio@e8a1b000arm,pl061arm,primecellTè¡°¤dÎÞ~š/ apb_pclkögpio@e8a1c000arm,pl061arm,primecellTè¡À¤eÎÞ~š0 apb_pclkögpio@ff3b4000arm,pl061arm,primecellTÿ;@¤fÎÞê1~š1 apb_pclkmö[UFS_REF_CLK][UFS_RST_N][SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS]GPIO_150_USER_LED1GPIO_151_USER_LED2Þ9gpio@ff3b5000arm,pl061arm,primecellTÿ;P¤gÎÞê1~š2 apb_pclköNCNCNCNCgpio@e8a1f000arm,pl061arm,primecellTè¡ð¤hÎÞê2~š3 apb_pclk@ö[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]gpio@e8a20000arm,pl061arm,primecellT袤iÎÞ~ê3š4 apb_pclk^ö[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3]gpio@fff0b000arm,pl061arm,primecellTÿð°¤jÎÞê4~š5 apb_pclkdö[GPIO_176_PMU_PWR_HOLD]NA[SYSCLK_EN]GPIO_179_WL_WAKEUP_APGPIO_180_HDMI_INTNAGPIO-F[I2C0_SCL]ÞEgpio@fff0c000arm,pl061arm,primecellTÿðÀ¤kÎÞê4~š5 apb_pclk^ö[I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C1_SCL][I2C1_SDA]GPIO_189_USER_LED3GPIO_190_USER_LED4Þngpio@fff0d000arm,pl061arm,primecellTÿðФlÎÞê4
~š5 apb_pclktö[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][GPIO_196_I2S2_DI][GPIO_197_I2S2_DO][GPIO_198_I2S2_XCLK][GPIO_199_I2S2_XFS]gpio@fff0e000arm,pl061arm,primecellTÿðà¤mÎÞ ê44~š5 apb_pclkzöNCNCGPIO_202_VBUS_TYPECGPIO_203_SD_DETGPIO_204_PMU12_IRQ_NGPIO_205_WIFI_ACTIVEGPIO_206_USBSW_SELGPIO_207_BT_ACTIVEÞ;gpio@fff0f000arm,pl061arm,primecellTÿðð¤nÎÞê4~š5 apb_pclkLöGPIO-AGPIO-BGPIO-CGPIO-DGPIO-E[PCIE_CLKREQ_N][PCIE_WAKE_N][SPI0_CLK]gpio@fff10000arm,pl061arm,primecellTÿñ¤oÎÞê4$~š5 apb_pclkBö[SPI0_DIN][SPI0_DOUT][SPI0_CS]GPIO_219_CC_INTNCNC[PMU_INT]Þ7gpio@fff1d000arm,pl061arm,primecellTÿñФÎÞ~š5 apb_pclköspi@ffd68000arm,pl022arm,primecellTÿÖ€+¤tš apb_pclk)default76
7AokayHLS-SPI0spi@ff3b3000arm,pl022arm,primecellTÿ;0+¤8š5 apb_pclk)default78
9AokayHHS-SPI1pcie@f4000000hisilicon,kirin960-pcie@Tôÿ?àóòõ dbiapbphyconfig +HpciÂö*~¤¾msi4ø€G(šRSQP:pcie_phy_refpcie_auxpcie_apb_phypcie_apb_syspcie_aclkU:ufs@ff3b0000#hisilicon,hi3660-ufsjedec,ufs-1.1 Tÿ;ÿ;¤šferef_clkphy_clka"„orstdwmmc1@ff37f000hisilicon,hi3660-dw-mshcTÿ7ð+¤‹šKciubiu0Ô"”oreset{5—ÈAokay©³ÄÑÞëù;)default7<�=>
?@dwmmc2@ff3ff000hisilicon,hi3660-dw-mshcTÿ?ð+¤ŒšLciubiu"”oreset—ÈAok©&4>)default7ABC
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ti,wl1837TE¤watchdog@e8a06000arm,sp805-wdtarm,primecellTè `¤,š apb_pclkwatchdog@e8a07000arm,sp805-wdtarm,primecellTè p¤-š apb_pclktsensor@fff30000hisilicon,hi3660-tsensorTÿó¤‘QÞFthermal-zonescls0gèud‹”Ftripstrip-point@0ýè¹èOpassivetrip-point@1$ø¹èOpassiveÞGcooling-mapsmap0ÄGÉ0Öÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1ÄGÉ0Öÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿetm@ecc40000"arm,coresight-etm4xarm,primecellTìÄš apb_pclkDout-portsportendpointåHÞMetm@ecd40000"arm,coresight-etm4xarm,primecellTìÔš apb_pclkDout-portsportendpointåIÞNetm@ece40000"arm,coresight-etm4xarm,primecellTìäš apb_pclkDout-portsportendpointåJÞOetm@ecf40000"arm,coresight-etm4xarm,primecellTìôš apb_pclkDout-portsportendpointåKÞPfunnel@ec801000+arm,coresight-dynamic-funnelarm,primecellT쀚 apb_pclkout-portsportendpointåLÞQin-ports+port@0TendpointåMÞHport@1TendpointåNÞIport@2TendpointåOÞJport@3TendpointåPÞKetf@ec802000 arm,coresight-tmcarm,primecellTì€ š apb_pclkin-portsportendpointåQÞLout-portsportendpointåRÞ_etm@ed440000"arm,coresight-etm4xarm,primecellTíDš apb_pclkDout-portsportendpointåSÞXetm@ed540000"arm,coresight-etm4xarm,primecellTíTš apb_pclkDout-portsportendpointåTÞYetm@ed640000"arm,coresight-etm4xarm,primecellTídš apb_pclkDout-portsportendpointåUÞZetm@ed740000"arm,coresight-etm4xarm,primecellTítš apb_pclkD out-portsportendpointåVÞ[funnel@ed001000+arm,coresight-dynamic-funnelarm,primecellTíš apb_pclkout-portsportendpointåWÞ\in-ports+port@0TendpointåXÞSport@1TendpointåYÞTport@2TendpointåZÞUport@3Tendpointå[ÞVetf@ed002000 arm,coresight-tmcarm,primecellTí š apb_pclkin-portsportendpointå\ÞWout-portsportendpointå]Þ`funnelarm,coresight-static-funnelš apb_pclkout-portsportendpointå^Þbin-ports+port@0Tendpointå_ÞRport@1Tendpointå`Þ]funnel@ec031000+arm,coresight-dynamic-funnelarm,primecellTìš apb_pclkout-portsportendpointåaÞcin-ports+port@0TendpointåbÞ^etf@ec036000 arm,coresight-tmcarm,primecellTì`š apb_pclkin-portsportendpointåcÞaout-portsportendpointådÞereplicator arm,coresight-static-replicatorš apb_pclkin-portsportendpointåeÞdout-ports+port@0TendpointåfÞhport@1TendpointågÞietr@ec033000 arm,coresight-tmcarm,primecellTì0š apb_pclkin-portsportendpointåhÞftpiu@ec032000!arm,coresight-tpiuarm,primecellTì š apb_pclkin-portsportendpointåiÞggpio-rangeõÞjpinmux@e896c000pinctrl-singleTè–Àð%7 U rjjtÞ0pmu_pmx_func Œcsi0_pwd_n_pmx_funcŒDcsi1_pwd_n_pmx_funcŒLisp0_pmx_funcŒXdhisp1_pmx_funcŒ\lppwr_key_pmx_funcŒ€Þki2c3_pmx_funcŒ,0Þi2c4_pmx_funcŒ”pcie_perstn_pmx_funcŒ\usbhub5734_pmx_funcŒ uart0_pmx_funcŒÌÐÞ uart1_pmx_func Œ°´¨¬Þ#uart2_pmx_func Œ¼ÀÈÄÞ%uart3_pmx_func ŒÜàäèÞ'uart4_pmx_func ŒìðôøÞ)uart5_pmx_func ŒÄȼÀÞ,uart6_pmx_func ŒÌÐÔØÞ.cam0_rst_pmx_funcŒÈcam1_rst_pmx_funcŒ$pinmux@ff37e000pinctrl-singleTÿ7à%7 UrjÞ2sd_pmx_func0ŒÞ<�pinmux@ff3b6000pinctrl-singleTÿ;`0%7 UrjÞ1ufs_pmx_funcŒspi3_pmx_func ŒÞ8pinmux@ff3fd000pinctrl-singleTÿ?Ð%7 UrjÞ3sdio_pmx_func0ŒÞApinmux@fff11000pinctrl-singleTÿñ¨%7 Urj*Þ4i2s2_pmx_func ŒDHLPslimbus_pmx_funcŒ,0i2c0_pmx_funcŒÞi2c1_pmx_funcŒ Þi2c7_pmx_funcŒ$(Þpcie_pmx_funcŒ„ˆspi2_pmx_func ŒŒ”˜Þ6i2s0_pmx_func Œ48<�@pinmux@e896c800pinconf-singleTè–È7 pmu_cfg_func Œ ½Ø ði2c3_cfg_funcŒ8<� ½ØðÞcsi0_pwd_n_cfg_funcŒP ½Øðcsi1_pwd_n_cfg_funcŒX ½Øðisp0_cfg_funcŒdpt ½Øðisp1_cfg_funcŒhx| ½Øðpwr_key_cfg_funcŒŒ ½ØðÞluart1_cfg_func Œ´¸¼À ½ØðÞ$uart2_cfg_func ŒÈÌÐÔ ½ØðÞ&uart5_cfg_func ŒÈÌÐÔ ½ØðÞ-cam0_rst_cfg_funcŒÔ ½Øðuart0_cfg_funcŒØÜ ½ØðÞ!uart6_cfg_func ŒØÜàä ½ØðÞ/uart3_cfg_func Œèìðô ½ØðÞ(uart4_cfg_func Œøü ½ØðÞ*cam1_rst_cfg_funcŒ0 ½Øðpinmux@ff3b6800pinconf-singleTÿ;h7 ufs_cfg_funcŒ ½Ø0ðspi3_cfg_funcŒ ½Øðpinmux@ff3fd800pinconf-singleTÿ?Ø7 sdio_clk_cfg_funcŒ ½ØððÞBsdio_cfg_func(Œ ½Ø€ðÞCpinmux@ff37e800pinconf-singleTÿ7è7 sd_clk_cfg_funcŒ ½ØððÞ=sd_cfg_func(Œ ½Ø€ðÞ>pinmux@fff11800pinconf-singleTÿñ¼7 i2c0_cfg_funcŒ ½ØðÞi2c1_cfg_funcŒ$( ½ØðÞi2c7_cfg_funcŒ,0 ½ØðÞslimbus_cfg_funcŒ48 ½Øði2s0_cfg_func Œ@DHL ½Øði2s2_cfg_func ŒPTX\ ½Øðpcie_cfg_funcŒ”˜ ½Øðspi2_cfg_func Œœ ¤¨ ½Øðusb_cfg_funcŒ¬ ½Øðaliasesö/soc/dwmmc1@ff37f000ü/soc/dwmmc2@ff3ff000/soc/serial@fdf02000
/soc/serial@fdf00000/soc/serial@fdf03000/soc/serial@ffd74000"/soc/serial@fdf01000*/soc/serial@fdf050002/soc/serial@fff32000chosen:serial6:115200n8memory@0HmemoryTreserved-memory+Âramoops@32000000ramoopsT2FR_reboot-mode-syscon@32100000sysconsimple-mfdT2reboot-modesyscon-reboot-modekrwfU~wfUŽwfUkeys
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µheartbeatuser_led2Hgreen:user2d9µnoneuser_led3Hgreen:user3dnµmmc0user_led4Hgreen:user4dn˵nonewlan_active_ledHyellow:wland;µphy0txÛoffbt_active_ledHblue:btd;µhci0-powerÛoffpmic@fff34000hisilicon,hi6421v530-pmicTÿó@~regulatorsLDO3éVOUT3_1V85øw@!‘À(xLDO9éVOUT9_1V8_2V95ø³ð2Z (ðÞ@LDO11éVOUT11_1V8_2V95ø³ð2Z (ðLDO15éVOUT15_3V0ø³ð-ÆÀDV(xLDO16éVOUT16_2V95ø³ð-ÆÀ(hÞ?wlan-en-1-8vregulator-fixedéwlan-en-regulatorøw@w@joop€ÞDfirmwareopteelinaro,optee-tz=smc compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachecpu-idle-statescapacity-dmips-mhzclocksoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityranges#clock-cells#reset-cellshisi,rst-syscon#mbox-cellsmboxesclock-namesclock-frequencyresetspinctrl-namespinctrl-0statuslabeldma-namesdmasenable-gpiosmax-speed#dma-cellsdma-channelsdma-requestsdma-channel-maskdma-no-ccidma-typeinterrupt-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesnum-cscs-gpiosreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapreset-gpiosfreq-table-hzreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthcap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104disable-wpcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcontributioncooling-deviceremote-endpoint#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathrecord-sizeconsole-sizeftrace-sizeoffsetmode-normalmode-bootloadermode-recoverywakeup-sourcelinux,codelinux,default-triggerpanic-indicatordefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-boot-onregulator-always-ongpiostartup-delay-usenable-active-high