Ð
þíB¸H>ô(Ä>¬€fsl,lx2160a-qdsfsl,lx2160a+7NXP Layerscape LX2160AQDScpus+cpu@0=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@1=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@100=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@101=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@200=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@201=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@300=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@301=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@400=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@401=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@500=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@Àº Ëcpu@501=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@Àº Ëcpu@600=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@Àº
Ëcpu@601=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@Àº
Ëcpu@700=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËcpu@701=cpuarm,cortex-a72IpsciW[b€o@€ŽÀ›@ÀºËl2-cache0cachedq@ƒÛçl2-cache1cachedq@ƒÛçl2-cache2cachedq@ƒÛçl2-cache3cachedq@ƒÛçl2-cache4cachedq@ƒÛçl2-cache5cachedq@ƒÛç l2-cache6cachedq@ƒÛç
l2-cache7cachedq@ƒÛçcpu-pw15arm,idle-stateïPW15ÿÐ'Ð7pçinterrupt-controller@6000000arm,gic-v3PW
H+Y`u çgic-its@6020000arm,gic-v3-its€Wçtimerarm,armv8-timer0u
pmuarm,cortex-a72-pmuupsci
arm,psci-0.2Psmcmemory@80000000=memoryW€€memory-controller@1080000fsl,qoriq-memory-controllerWumemory-controller@1090000fsl,qoriq-memory-controllerW usysclkfixed-clockªõáºsysclkçsocsimple-bus+YÍcrypto@8000000fsl,sec-v5.0fsl,sec-v4.0Ø
+YWu‹äñokayjr@10000,fsl,sec-v5.0-job-ringfsl,sec-v4.0-job-ringWuŒjr@20000,fsl,sec-v5.0-job-ringfsl,sec-v4.0-job-ringWujr@30000,fsl,sec-v5.0-job-ringfsl,sec-v4.0-job-ringWuŽjr@40000,fsl,sec-v5.0-job-ringfsl,sec-v4.0-job-ringWuclock-controller@1300000fsl,lx2160a-clockgenW0
[çsyscon@1e00000fsl,lx2160a-dcfgsysconWài2c@2000000fsl,vf610-i2c+Wu"øi2c[
ñokayi2c-mux@77nxp,pca9547Ww+i2c@2+Wpower-monitor@40
ti,ina220W@
ôpower-monitor@41
ti,ina220WA
èi2c@3+Wtemperature-sensor@4cnxp,sa56004WLtemperature-sensor@4dnxp,sa56004WMrtc@51nxp,pcf2129WQi2c@2010000fsl,vf610-i2c+Wu"øi2c[ ñdisabledi2c@2020000fsl,vf610-i2c+Wu#øi2c[ ñdisabledi2c@2030000fsl,vf610-i2c+Wu#øi2c[ ñdisabledi2c@2040000fsl,vf610-i2c+WuJøi2c[
ñdisabledi2c@2050000fsl,vf610-i2c+WuJøi2c[ ñdisabledi2c@2060000fsl,vf610-i2c+WuKøi2c[ ñdisabledi2c@2070000fsl,vf610-i2c+WuKøi2c[ ñdisabledspi@20c0000nxp,lx2160a-fspi+ W 'fspi_basefspi_mmapu[
øfspi_enfspi ñdisabledesdhc@2140000
fsl,esdhcWu[1ää@Qñokayesdhc@2150000
fsl,esdhcWu?[1ää@[Qñokayserial@21c0000arm,sbsa-uartarm,pl011Wu eÂñokayserial@21d0000arm,sbsa-uartarm,pl011Wu!eÂñokayserial@21e0000arm,sbsa-uartarm,pl011WuHe ñdisabledserial@21f0000arm,sbsa-uartarm,pl011WuIe ñdisabledgpio@2300000fsl,qoriq-gpioW0u$sƒ`Hgpio@2310000fsl,qoriq-gpioW1u$sƒ`Hgpio@2320000fsl,qoriq-gpioW2u%sƒ`Hç
gpio@2330000fsl,qoriq-gpioW3u%sƒ`Hwatchdog@23a0000arm,sbsa-gwdt W:9u;usb@3100000
snps,dwc3WuP›host£ Æàñokayusb@3110000
snps,dwc3WuQ›host£ Æàñokaysata@3200000fsl,lx2160a-ahci W 'ahcisata-eccu…[äñokaysata@3210000fsl,lx2160a-ahci W! 'ahcisata-eccuˆ[äñokaysata@3220000fsl,lx2160a-ahci W" 'ahcisata-eccua[äñokaysata@3230000fsl,lx2160a-ahci W# 'ahcisata-eccud[äñokayiommu@5000000arm,mmu-500W€
¨u
ÓÔÕÖ×ØÙÚÛÜ’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑäçconsole@8340020fsl,dpaa2-consoleW4 ptp-timer@8b95000fsl,dpaa2-ptpW¹P[ fsl-mc@80c000000
fsl,qoriq-mc W@4/:ä+0Ydpmacs+dpmac@1fsl,qoriq-mc-dpmacWdpmac@2fsl,qoriq-mc-dpmacWdpmac@3fsl,qoriq-mc-dpmacWdpmac@4fsl,qoriq-mc-dpmacWdpmac@5fsl,qoriq-mc-dpmacWdpmac@6fsl,qoriq-mc-dpmacWdpmac@7fsl,qoriq-mc-dpmacWdpmac@8fsl,qoriq-mc-dpmacWdpmac@9fsl,qoriq-mc-dpmacW dpmac@afsl,qoriq-mc-dpmacW
dpmac@bfsl,qoriq-mc-dpmacWdpmac@cfsl,qoriq-mc-dpmacWdpmac@dfsl,qoriq-mc-dpmacW
dpmac@efsl,qoriq-mc-dpmacWdpmac@ffsl,qoriq-mc-dpmacWdpmac@10fsl,qoriq-mc-dpmacWdpmac@11fsl,qoriq-mc-dpmacWdpmac@12fsl,qoriq-mc-dpmacWaliasesD/soc/crypto@8000000K/soc/serial@21c0000chosenSserial0:115200n8regulator-sb3v3regulator-fixed_MC34717-3.3VSBn2Z †2Z ž°ç compatibleinterrupt-parent#address-cells#size-cellsmodeldevice_typeenable-methodregclocksd-cache-sized-cache-line-sized-cache-setsi-cache-sizei-cache-line-sizei-cache-setsnext-level-cachecpu-idle-statescache-levelphandleidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-us#interrupt-cellsrangesinterrupt-controllerinterruptsmsi-controllerlittle-endian#clock-cellsclock-frequencyclock-output-namesdma-rangesfsl,sec-eradma-coherentstatusclock-namesscl-gpioshunt-resistorvcc-supplyreg-namesvoltage-rangessdhci,auto-cmd12bus-widthbroken-cdcurrent-speedgpio-controller#gpio-cellstimeout-secdr_modesnps,quirk-frame-length-adjustmentsnps,dis_rxdet_inp3_quirksnps,incr-burst-type-adjustment#iommu-cells#global-interruptsfsl,extts-fifomsi-parentiommu-mapcryptoserial0stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-on