Ð þí™8˜(`"amd,seattle-overdriveamd,seattle +37AMD Seattle (Rev.B1) Development Board (Overdrive)interrupt-controller@e1101000arm,gic-400arm,cortex-a15-gic=R+@cááð á á  g ráyv2m@e0080000arm,gic-v2m-framecytimerarm,armv8-timer0g ÿÿ ÿ ÿpmuarm,armv8-pmuv3`g     smb simple-bus+rclk100mhz_0 fixed-clock›¨õá¸adl3clk_100mhzclk375mhz fixed-clock›¨Z À¸ccpclk_375mhzclk333mhz fixed-clock›¨Ù-@¸sataclk_333mhzyclk500mhz_0 fixed-clock›¨Íe¸pcieclk_500mhzclk500mhz_1 fixed-clock›¨Íe¸dmaclk_500mhzclk250mhz_4 fixed-clock›¨æ²€¸miscclk_250mhzyclk100mhz_1 fixed-clock›¨õá¸uartspiclk_100mhzysata@e0300000snps,dwc-ahcicà0 gcËÒsata@e0d00000ßoksnps,dwc-ahcicàÐ gbËÒi2c@e1000000ßoksnps,designware-i2ccá geËi2c@e0050000ßoksnps,designware-i2ccà gTËserial@e1010000arm,pl011arm,primecellcá gHËæuartclkapb_pclkspi@e1020000ßokarm,pl022arm,primecellcáò gJË æapb_pclkspi@e1030000ßokarm,pl022arm,primecellcáò gIË æapb_pclk+sdcard@0 mmc-spi-slotc1- € H)9IXlgpio@e1040000 ßdisabledarm,pl061arm,primecell€cጠgg=RË æapb_pclkgpio@e1050000ßokarm,pl061arm,primecell€cáŒ=R gfË æapb_pclkgpio@e0020000ßokarm,pl061arm,primecell€càŒ=R gnË æapb_pclkgpio@e0030000ßokarm,pl061arm,primecell€càŒ=R gmË æapb_pclkgpio@e0080000ßokarm,pl061arm,primecell€càŒ=R giË æapb_pclkccp@e0100000ßokamd,ccp-seattle-v1acà gÒœpcie@f0000000pci-host-ecam-generic+R­pci¹ÃcðÎø á !"#ҐCTrïÿ@@€ßokccn@e8000000 arm,ccn-504cè g|kcs@e0010000ßok ipmi-kcs­ipmicà g…ïøclk250mhz_0 fixed-clock›¨æ²€¸xgmacclk0_dma_250mhzyclk250mhz_1 fixed-clock›¨æ²€¸xgmacclk0_ptp_250mhzyclk250mhz_2 fixed-clock›¨æ²€¸xgmacclk1_dma_250mhzyclk250mhz_3 fixed-clock›¨æ²€¸xgmacclk1_ptp_250mhzy xgmac@e0700000amd,xgbe-seattle-v1aPcàpàxá$á%`á%øHgEZ[\]C , <� P  c u ©¡¢£¤¥Ëædma_clkptp_clkµxgmii¾Òy xgmac@e0900000amd,xgbe-seattle-v1aPcàà˜á$ á%€`á%üHgDUVWXB , <� P  c u ©±²³´µË ædma_clkptp_clkµxgmii¾Òy smmu@e0600000 arm,mmu-401cà`ÏgPPDâ smmu@e0800000 arm,mmu-401cà€ÏgOODâ chosenî/smb/serial@e1010000psci arm,psci-0.2úsmc compatibleinterrupt-parent#address-cells#size-cellsmodelinterrupt-controller#interrupt-cellsreginterruptsrangesphandlemsi-controllerdma-ranges#clock-cellsclock-frequencyclock-output-namesclocksdma-coherentstatusclock-namesspi-controllernum-csspi-max-frequencyvoltage-rangespl022,hierarchypl022,interfacepl022,com-modepl022,rx-level-trigpl022,tx-level-trig#gpio-cellsgpio-controlleramd,zlib-supportdevice_typebus-rangemsi-parentinterrupt-map-maskinterrupt-mapreg-sizereg-spacingamd,per-channel-interruptamd,speed-setamd,serdes-blwcamd,serdes-cdr-rateamd,serdes-pq-skewamd,serdes-tx-ampamd,serdes-dfe-tap-configamd,serdes-dfe-tap-enablemac-addressphy-mode#stream-id-cells#global-interruptsmmu-mastersstdout-pathmethod