Ð þí™8¨(\pnetxeon,r89rockchip,rk3288& 7Netxeon R89aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000‚/i2c@ff140000‡/i2c@ff660000Œ/i2c@ff150000‘/i2c@ff160000–/i2c@ff170000›/mmc@ff0f0000¡/mmc@ff0c0000§/mmc@ff0d0000­/mmc@ff0e0000³/serial@ff180000»/serial@ff190000Ã/serial@ff690000Ë/serial@ff1b0000Ó/serial@ff1c0000Û/spi@ff110000à/spi@ff120000å/spi@ff130000arm-pmuarm,cortex-a12-pmu0ê—˜™šõcpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@501#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@502#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@503#cpuarm,cortex-a12/3:N]œ@krrŒ —opp-table-0operating-points-v2Ÿ—opp-126000000ª‚›€± » opp-216000000ª ßæ± » opp-312000000ª˜¾± » opp-408000000ªQ–± » opp-600000000ª#ÃF± » opp-696000000ª)|±~ðopp-816000000ª0£,±B@opp-1008000000ª<ܱopp-1200000000ªG†Œ±Èàopp-1416000000ªTfr±O€opp-1512000000ªZJ±Ö opp-1608000000ª_Ø"±™preserved-memory¿dma-unusable@fe000000/þoscillator fixed-clockÆn6Öxin24mé— timerarm,armv7-timerö0ê   Æn6timer@ff810000rockchip,rk3288-timer/ÿ  êH ka  1pclktimerdisplay-subsystemrockchip,display-subsystem= mmc@ff0c0000rockchip,rk3288-dw-mshcCðÑ€ kÈDrv1biuciuciu-driveciu-sampleQ ê /ÿ @3€\resethokayoy‹œÈ®¹defaultÇ ÑÝmmc@ff0d0000rockchip,rk3288-dw-mshcCðÑ€ kÉEsw1biuciuciu-driveciu-sampleQ ê!/ÿ @3\reset hdisabledmmc@ff0e0000rockchip,rk3288-dw-mshcCðÑ€ kÊFtx1biuciuciu-driveciu-sampleQ ê"/ÿ@3‚\reset hdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcCðÑ€ kËGuy1biuciuciu-driveciu-sampleQ ê#/ÿ@3ƒ\reset hdisabledsaradc@ff100000rockchip,saradc/ÿ ê$êkI[1saradcapb_pclk3W \saradc-apbhokayüspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR1spiclkapb_pclk   txrx ê,¹defaultÇ/ÿ hdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS1spiclkapb_pclk  txrx ê-¹defaultÇ/ÿ hdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT1spiclkapb_pclk txrx ê.¹defaultÇ /ÿ hdisabledi2c@ff140000rockchip,rk3288-i2c/ÿ ê>1i2ckM¹defaultÇ! hdisabledi2c@ff150000rockchip,rk3288-i2c/ÿ ê?1i2ckO¹defaultÇ" hdisabledi2c@ff160000rockchip,rk3288-i2c/ÿ ê@1i2ckP¹defaultÇ# hdisabledi2c@ff170000rockchip,rk3288-i2c/ÿ êA1i2ckQ¹defaultÇ$hokayserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê7!kMU1baudclkapb_pclk txrx¹defaultÇ%hokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê8!kNV1baudclkapb_pclk txrx¹defaultÇ&hokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿi ê9!kOW1baudclkapb_pclk¹defaultÇ'hokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê:!kPX1baudclkapb_pclk txrx¹defaultÇ(hokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê;!kQY1baudclkapb_pclk   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generic-ehci/ÿ\ êkÄ hdisableddma-controller@ff600000arm,pl330arm,primecell/ÿ`@ê.9TkÁ 1apb_pclk hdisabledi2c@ff650000rockchip,rk3288-i2c/ÿe ê<�1i2ckL¹defaultÇ9hokaypmic@40silergy,syr827/@MjVDD_CPUy,• øP­™pÅ@Úî:— pmic@41silergy,syr828/AMjVDD_GPUy,• øP­™pÅ@Úî:rtc@51haoyu,hym8563/QéÖxin32k&;ê¹defaultÇ<�pmic@5aactive-semi,act8846/Z¹defaultÇ=> regulatorsREG1jVCC_DDR•O€­O€ÚREG2jVCC_IO•2Z ­2Z Ú—wREG3jVDD_LOG•B@­B@ÚREG4jVCC_20•„€­„€ÚREG5 jVCCIO_SD•2Z ­2Z Ú—REG6 jVDD10_LCD•B@­B@ÚREG7jVCC_WL•2Z ­2Z ÚREG8jVCCA_33•2Z ­2Z ÚREG9jVCC_LAN•2Z ­2Z Ú—2REG10jVDD_10•B@­B@ÚREG11jVCC_18•w@­w@Ú—REG12 jVCC18_LCD•w@­w@Úi2c@ff660000rockchip,rk3288-i2c/ÿf ê=1i2ckN¹defaultÇ? hdisabledpwm@ff680000rockchip,rk3288-pwm/ÿh#¹defaultÇ@k_hokaypwm@ff680010rockchip,rk3288-pwm/ÿh#¹defaultÇAk_ hdisabledpwm@ff680020rockchip,rk3288-pwm/ÿh #¹defaultÇBk_ hdisabledpwm@ff680030rockchip,rk3288-pwm/ÿh0#¹defaultÇCk_ hdisabledsram@ff700000 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hdisabledportsport@0/endpoint@0/6`—Yendpoint@1/6a—^port@1/lvds@ff96c000rockchip,rk3288-lvds/ÿ–À@kg 1pclk_lvds¹lcdcÇb!U ô1 hdisabledportsport@0/endpoint@0/6c—Zendpoint@1/6d—_port@1/dp@ff970000rockchip,rk3288-dp/ÿ—@ êbkic1dppclkïeôdp!U 3o\dpô1 hdisabledportsport@0/endpoint@0/6f—Xendpoint@1/6g—]port@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/ÿ˜! êgkhmn1iahbisfrcec!U ô1³hokayportsport@0/endpoint@0/6h—Wendpoint@1/6i—\port@1/video-codec@ff9a0000rockchip,rk3288-vpu/ÿšê   JvepuvdpukÐÜ 1aclkhclk/j!U iommu@ff9a0800rockchip,iommu/ÿš ê kÐÜ 1aclkifaceù!U —jiommu@ff9c0440rockchip,iommu /ÿœ@@ÿœ€@ êokÏÛ 1aclkifaceù hdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/ÿ£$ê JjobmmugpukÀ:kN!U  hdisabled—.opp-table-1operating-points-v2—kopp-100000000ªõá±~ðopp-200000000ª ë±~ðopp-300000000ªá£±B@opp-400000000ªׄ±Èàopp-600000000ª#ÃF±Ðqos@ffaa0000rockchip,rk3288-qossyscon/ÿª —Pqos@ffaa0080rockchip,rk3288-qossyscon/ÿª€ —Qqos@ffad0000rockchip,rk3288-qossyscon/ÿ­ —Eqos@ffad0100rockchip,rk3288-qossyscon/ÿ­ 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êWkFl|F[gpio@ff7e0000rockchip,gpio-bank/ÿ~ êXkGl|F[—sgpio@ff7f0000rockchip,gpio-bank/ÿ êYkHl|F[hdmihdmi-cec-c0ˆlhdmi-cec-c7ˆlhdmi-ddc ˆllhdmi-ddc-unwedge ˆmlpcfg-output-low–—mpcfg-pull-up¡—npcfg-pull-down®—opcfg-pull-none½—lpcfg-pull-none-12ma½Ê —psuspendglobal-pwroffˆlddrio-pwroffˆlddr0-retentionˆnddr1-retentionˆnedpedp-hpdˆ oi2c0i2c0-xfer ˆll—9i2c1i2c1-xfer ˆll—!i2c2i2c2-xfer ˆ l l—?i2c3i2c3-xfer ˆll—"i2c4i2c4-xfer ˆll—#i2c5i2c5-xfer ˆll—$i2s0i2s0-bus`ˆllllll—Tlcdclcdc-ctl@ˆllll—bsdmmcsdmmc-clkˆl— sdmmc-cmdˆn—sdmmc-cdˆn—sdmmc-bus1ˆnsdmmc-bus4@ˆnnnn—sdio0sdio0-bus1ˆnsdio0-bus4@ˆnnnnsdio0-cmdˆnsdio0-clkˆlsdio0-cdˆnsdio0-wpˆnsdio0-pwrˆnsdio0-bkpwrˆnsdio0-intˆnsdio1sdio1-bus1ˆnsdio1-bus4@ˆnnnnsdio1-cdˆnsdio1-wpˆnsdio1-bkpwrˆnsdio1-intˆnsdio1-cmdˆnsdio1-clkˆlsdio1-pwrˆ nemmcemmc-clkˆlemmc-cmdˆnemmc-pwrˆ nemmc-bus1ˆnemmc-bus4@ˆnnnnemmc-bus8€ˆnnnnnnnnspi0spi0-clkˆ n—spi0-cs0ˆ n—spi0-txˆn—spi0-rxˆn—spi0-cs1ˆnspi1spi1-clkˆ n—spi1-cs0ˆ n—spi1-rxˆn—spi1-txˆn—spi2spi2-cs1ˆnspi2-clkˆn—spi2-cs0ˆn— spi2-rxˆn—spi2-txˆ n—uart0uart0-xfer ˆnl—%uart0-ctsˆnuart0-rtsˆluart1uart1-xfer ˆn l—&uart1-ctsˆ nuart1-rtsˆ luart2uart2-xfer ˆnl—'uart3uart3-xfer ˆnl—(uart3-ctsˆ nuart3-rtsˆ luart4uart4-xfer ˆnl—)uart4-ctsˆ nuart4-rtsˆ ltsadcotp-pinˆ l—/otp-outˆ l—0pwm0pwm0-pinˆl—@pwm1pwm1-pinˆl—Apwm2pwm2-pinˆl—Bpwm3pwm3-pinˆl—Cgmacrgmii-pinsðˆllllpppplll ppll—5rmii-pins ˆllllllllllspdifspdif-txˆ l—Spcfg-output-highÙ—qact8846pmic-vselˆm—=pwr-holdˆq—>buttonspwrbtnˆn—ririr-intˆn—tpmicpmic-intˆn—<�usbhost-vbus-drvˆl—uotg-vbus-drvˆ l—vmemory@0#memory/€external-gmac-clock fixed-clockÆsY@ Öext_gmacé—4gpio-keys gpio-keyså¹defaultÇrkey-power ð;ötGPIO Key Power&dir-receivergpio-ir-receiver ðs¹defaultÇtvcc-host-regulatorregulator-fixed8 †;¹defaultÇu jvcc_hostÚîvcc-otg-regulatorregulator-fixed8 †; ¹defaultÇvjvcc_otgÚîsdmmc-regulatorregulator-fixed jsdmmc-supply•2Z ­2Z  †s K† w—sys-regulatorregulator-fixed jsys-supply•LK@­LK@Úî—: #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supply#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplysystem-power-controller#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervalenable-active-highstartup-delay-us