Ð
þí™8¨(\pnetxeon,r89rockchip,rk3288&7Netxeon R89aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000‚/i2c@ff140000‡/i2c@ff660000Œ/i2c@ff150000‘/i2c@ff160000–/i2c@ff170000›/mmc@ff0f0000¡/mmc@ff0c0000§/mmc@ff0d0000/mmc@ff0e0000³/serial@ff180000»/serial@ff190000Ã/serial@ff690000Ë/serial@ff1b0000Ó/serial@ff1c0000Û/spi@ff110000à/spi@ff120000å/spi@ff130000arm-pmuarm,cortex-a12-pmu0ê—˜™šõcpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@501#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@502#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@503#cpuarm,cortex-a12/3:N]œ@krrŒ —opp-table-0operating-points-v2Ÿ—opp-126000000ª‚›€±
» opp-216000000ªßæ±
» opp-312000000ª˜¾±
» opp-408000000ªQ–±
» opp-600000000ª#ÃF±
» opp-696000000ª)|±~ðopp-816000000ª0£,±B@opp-1008000000ª<ܱopp-1200000000ªG†Œ±Èàopp-1416000000ªTfr±O€opp-1512000000ªZJ±Ö opp-1608000000ª_Ø"±™preserved-memory¿dma-unusable@fe000000/þoscillatorfixed-clockÆn6Öxin24mé—
timerarm,armv7-timerö0ê
Æn6timer@ff810000rockchip,rk3288-timer/ÿ êHka
1pclktimerdisplay-subsystemrockchip,display-subsystem=mmc@ff0c0000rockchip,rk3288-dw-mshcCðÑ€ kÈDrv1biuciuciu-driveciu-sampleQê /ÿ@3€\resethokayoy‹œÈ®¹defaultÇ
ÑÝmmc@ff0d0000rockchip,rk3288-dw-mshcCðÑ€ kÉEsw1biuciuciu-driveciu-sampleQê!/ÿ
@3\reset hdisabledmmc@ff0e0000rockchip,rk3288-dw-mshcCðÑ€ kÊFtx1biuciuciu-driveciu-sampleQê"/ÿ@3‚\reset hdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcCðÑ€ kËGuy1biuciuciu-driveciu-sampleQê#/ÿ@3ƒ\reset hdisabledsaradc@ff100000rockchip,saradc/ÿê$êkI[1saradcapb_pclk3W\saradc-apbhokayüspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR1spiclkapb_pclk
txrxê,¹defaultÇ/ÿ hdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS1spiclkapb_pclk
txrxê-¹defaultÇ/ÿ hdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT1spiclkapb_pclk
txrxê.¹defaultÇ /ÿ hdisabledi2c@ff140000rockchip,rk3288-i2c/ÿê>1i2ckM¹defaultÇ! hdisabledi2c@ff150000rockchip,rk3288-i2c/ÿê?1i2ckO¹defaultÇ" hdisabledi2c@ff160000rockchip,rk3288-i2c/ÿê@1i2ckP¹defaultÇ# hdisabledi2c@ff170000rockchip,rk3288-i2c/ÿêA1i2ckQ¹defaultÇ$hokayserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿê7!kMU1baudclkapb_pclk
txrx¹defaultÇ%hokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿê8!kNV1baudclkapb_pclk
txrx¹defaultÇ&hokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿiê9!kOW1baudclkapb_pclk¹defaultÇ'hokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿê:!kPX1baudclkapb_pclk
txrx¹defaultÇ(hokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿê;!kQY1baudclkapb_pclk
txrx¹defaultÇ)hokaydma-controller@ff250000arm,pl330arm,primecell/ÿ%@ê.9Tk 1apb_pclk—thermal-zonesreserve-thermalkèˆ*cpu-thermalkdˆ*tripscpu_alert0Ÿp«Ð*passive—+cpu_alert1Ÿ$ø«Ð*passive—,cpu_critŸ_«Ð *criticalcooling-mapsmap0¶+0»ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1¶,0»ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermalkdˆ*tripsgpu_alert0Ÿp«Ð*passive—-gpu_critŸ_«Ð *criticalcooling-mapsmap0¶-».ÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadc/ÿ(ê%kHZ1tsadcapb_pclk3Ÿ
\tsadc-apb¹initdefaultsleepÇ/Ê0Ô/Þô1shokay/—*ethernet@ff290000rockchip,rk3288-gmac/ÿ)êJmacirqeth_wake_irqô18k—fgc˜Ä]M1stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B
\stmmacethhokayZ2ergmiininput{3‹¡'B@¶—Æ4¹defaultÇ5Ý0æusb@ff500000
generic-ehci/ÿPêkÂï6ôusbhokayusb@ff520000
generic-ohci/ÿRê)kÂï6ôusb hdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿTêkÃ1otgþhostï7 ôusb2-phyhokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿXêkÁ1otgþotg/>€€@@ ï8 ôusb2-phyhokayusb@ff5c0000
generic-ehci/ÿ\êkÄ hdisableddma-controller@ff600000arm,pl330arm,primecell/ÿ`@ê.9TkÁ 1apb_pclk hdisabledi2c@ff650000rockchip,rk3288-i2c/ÿeê<�1i2ckL¹defaultÇ9hokaypmic@40silergy,syr827/@MjVDD_CPUy,•øP™pÅ@Úî:— pmic@41silergy,syr828/AMjVDD_GPUy,•øP™pÅ@Úî:rtc@51haoyu,hym8563/QéÖxin32k&;ê¹defaultÇ<�pmic@5aactive-semi,act8846/Z¹defaultÇ=>regulatorsREG1jVCC_DDR•O€O€ÚREG2jVCC_IO•2Z 2Z Ú—wREG3jVDD_LOG•B@B@ÚREG4jVCC_20•„€„€ÚREG5 jVCCIO_SD•2Z 2Z Ú—REG6
jVDD10_LCD•B@B@ÚREG7jVCC_WL•2Z 2Z ÚREG8jVCCA_33•2Z 2Z ÚREG9jVCC_LAN•2Z 2Z Ú—2REG10jVDD_10•B@B@ÚREG11jVCC_18•w@w@Ú—REG12
jVCC18_LCD•w@w@Úi2c@ff660000rockchip,rk3288-i2c/ÿfê=1i2ckN¹defaultÇ? hdisabledpwm@ff680000rockchip,rk3288-pwm/ÿh#¹defaultÇ@k_hokaypwm@ff680010rockchip,rk3288-pwm/ÿh#¹defaultÇAk_ hdisabledpwm@ff680020rockchip,rk3288-pwm/ÿh #¹defaultÇBk_ hdisabledpwm@ff680030rockchip,rk3288-pwm/ÿh0#¹defaultÇCk_ hdisabledsram@ff700000
mmio-sram/ÿp€¿ÿp€smp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/ÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/ÿs—power-controller!rockchip,rk3288-power-controller.¶hÆ
—Upower-domain@9/ ÈkÊÍÈÌÅƾ¿ÔÕÖÙÑÒchgfdehilkj$BDEFGHIJKL.power-domain@11/kÏopBMN.power-domain@12/kÐÜBO.power-domain@13/
kÀBPQ.reboot-modesyscon-reboot-modeI”PRBÃ\RBÃjRBÃ zRBÃsyscon@ff740000rockchip,rk3288-sgrfsyscon/ÿtclock-controller@ff760000rockchip,rk3288-cru/ÿvk
1xin24mô1é†H¶ÑÝjÒÞk$“#g¸€×„Íeá£ðÑ€xhÀá£ðÑ€xhÀ—syscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/ÿw—1edp-phyrockchip,rk3288-dp-phykh124m¨ hdisabled—eio-domains"rockchip,rk3288-io-voltage-domain hdisabledusbphyrockchip,rk3288-usb-phyhokayusb-phy@320¨/ k]1phyclké3…
\phy-reset—8usb-phy@334¨/4k^1phyclké3ˆ
\phy-reset—6usb-phy@348¨/Hk_1phyclké3‹
\phy-reset—7watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/ÿ€kpêOhokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/ÿ‹³kTÐ
1mclkhclkR
txê6¹defaultÇSô1 hdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ÿ‰³ê5kRÎ1i2s_clki2s_hclkRR
txrx¹defaultÇTÄß hdisabledcrypto@ff8a0000rockchip,rk3288-crypto/ÿŠ@ê0 kÇÍ}Á1aclkhclksclkapb_pclk3®\crypto-rstiommu@ff900800rockchip,iommu/ÿ@êkÊÔ1aclkifaceù hdisablediommu@ff914000rockchip,iommu /ÿ‘@ÿ‘PêkÍÕ1aclkifaceù hdisabledrga@ff920000rockchip,rk3288-rga/ÿ’€êkÈÖj1aclkhclksclk!U 3ilm
\coreaxiahbvop@ff930000rockchip,rk3288-vop /ÿ“œÿ“êkžÑ1aclk_vopdclk_vophclk_vop!U 3def
\axiahbdclk/Vhokayport—endpoint@0/6W—hendpoint@1/6X—fendpoint@2/6Y—`endpoint@3/6Z—ciommu@ff930300rockchip,iommu/ÿ“êkÅÑ1aclkiface!U ùhokay—Vvop@ff940000rockchip,rk3288-vop /ÿ”œÿ”êkÆ¿Ò1aclk_vopdclk_vophclk_vop!U 3°±²
\axiahbdclk/[hokayport—endpoint@0/6\—iendpoint@1/6]—gendpoint@2/6^—aendpoint@3/6_—diommu@ff940300rockchip,iommu/ÿ”êkÆÒ1aclkiface!U ùhokay—[dsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/ÿ–@êk~d 1refpclk!U ô1 hdisabledportsport@0/endpoint@0/6`—Yendpoint@1/6a—^port@1/lvds@ff96c000rockchip,rk3288-lvds/ÿ–À@kg
1pclk_lvds¹lcdcÇb!U ô1 hdisabledportsport@0/endpoint@0/6c—Zendpoint@1/6d—_port@1/dp@ff970000rockchip,rk3288-dp/ÿ—@êbkic1dppclkïeôdp!U 3o\dpô1 hdisabledportsport@0/endpoint@0/6f—Xendpoint@1/6g—]port@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/ÿ˜!êgkhmn1iahbisfrcec!U ô1³hokayportsport@0/endpoint@0/6h—Wendpoint@1/6i—\port@1/video-codec@ff9a0000rockchip,rk3288-vpu/ÿšê
JvepuvdpukÐÜ
1aclkhclk/j!Uiommu@ff9a0800rockchip,iommu/ÿšêkÐÜ1aclkifaceù!U—jiommu@ff9c0440rockchip,iommu /ÿœ@@ÿœ€@êokÏÛ1aclkifaceù hdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/ÿ£$êJjobmmugpukÀ:kN!U
hdisabled—.opp-table-1operating-points-v2—kopp-100000000ªõá±~ðopp-200000000ªë±~ðopp-300000000ªá£±B@opp-400000000ª×„±Èàopp-600000000ª#ÃF±Ðqos@ffaa0000rockchip,rk3288-qossyscon/ÿª —Pqos@ffaa0080rockchip,rk3288-qossyscon/ÿª€ —Qqos@ffad0000rockchip,rk3288-qossyscon/ÿ —Eqos@ffad0100rockchip,rk3288-qossyscon/ÿ —Fqos@ffad0180rockchip,rk3288-qossyscon/ÿ€ —Gqos@ffad0400rockchip,rk3288-qossyscon/ÿ —Hqos@ffad0480rockchip,rk3288-qossyscon/ÿ€ —Iqos@ffad0500rockchip,rk3288-qossyscon/ÿ —Dqos@ffad0800rockchip,rk3288-qossyscon/ÿ —Jqos@ffad0880rockchip,rk3288-qossyscon/ÿ€ —Kqos@ffad0900rockchip,rk3288-qossyscon/ÿ —Lqos@ffae0000rockchip,rk3288-qossyscon/ÿ® —Oqos@ffaf0000rockchip,rk3288-qossyscon/ÿ¯ —Mqos@ffaf0080rockchip,rk3288-qossyscon/ÿ¯€ —Ndma-controller@ffb20000arm,pl330arm,primecell/ÿ²@ê.9TkÁ 1apb_pclk—Refuse@ffb40000rockchip,rk3288-efuse/ÿ´ kq1pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000arm,gic-400F[@/ÿÀÿÀ ÿÀ@ ÿÀ` ê —pinctrlrockchip,rk3288-pinctrlô1¿gpio@ff750000rockchip,gpio-bank/ÿuêQk@l|F[—;gpio@ff780000rockchip,gpio-bank/ÿxêRkAl|F[gpio@ff790000rockchip,gpio-bank/ÿyêSkBl|F[gpio@ff7a0000rockchip,gpio-bank/ÿzêTkCl|F[gpio@ff7b0000rockchip,gpio-bank/ÿ{êUkDl|F[—3gpio@ff7c0000rockchip,gpio-bank/ÿ|êVkEl|F[gpio@ff7d0000rockchip,gpio-bank/ÿ}êWkFl|F[gpio@ff7e0000rockchip,gpio-bank/ÿ~êXkGl|F[—sgpio@ff7f0000rockchip,gpio-bank/ÿêYkHl|F[hdmihdmi-cec-c0ˆlhdmi-cec-c7ˆlhdmi-ddc ˆllhdmi-ddc-unwedge ˆmlpcfg-output-low–—mpcfg-pull-up¡—npcfg-pull-down®—opcfg-pull-none½—lpcfg-pull-none-12ma½Ê—psuspendglobal-pwroffˆlddrio-pwroffˆlddr0-retentionˆnddr1-retentionˆnedpedp-hpdˆoi2c0i2c0-xfer ˆll—9i2c1i2c1-xfer ˆll—!i2c2i2c2-xfer ˆ l
l—?i2c3i2c3-xfer ˆll—"i2c4i2c4-xfer ˆll—#i2c5i2c5-xfer ˆll—$i2s0i2s0-bus`ˆllllll—Tlcdclcdc-ctl@ˆllll—bsdmmcsdmmc-clkˆl—
sdmmc-cmdˆn—sdmmc-cdˆn—sdmmc-bus1ˆnsdmmc-bus4@ˆnnnn—sdio0sdio0-bus1ˆnsdio0-bus4@ˆnnnnsdio0-cmdˆnsdio0-clkˆlsdio0-cdˆnsdio0-wpˆnsdio0-pwrˆnsdio0-bkpwrˆnsdio0-intˆnsdio1sdio1-bus1ˆnsdio1-bus4@ˆnnnnsdio1-cdˆnsdio1-wpˆnsdio1-bkpwrˆnsdio1-intˆnsdio1-cmdˆnsdio1-clkˆlsdio1-pwrˆ nemmcemmc-clkˆlemmc-cmdˆnemmc-pwrˆ nemmc-bus1ˆnemmc-bus4@ˆnnnnemmc-bus8€ˆnnnnnnnnspi0spi0-clkˆn—spi0-cs0ˆ
n—spi0-txˆn—spi0-rxˆn—spi0-cs1ˆnspi1spi1-clkˆn—spi1-cs0ˆ
n—spi1-rxˆn—spi1-txˆn—spi2spi2-cs1ˆnspi2-clkˆn—spi2-cs0ˆn— spi2-rxˆn—spi2-txˆ n—uart0uart0-xfer ˆnl—%uart0-ctsˆnuart0-rtsˆluart1uart1-xfer ˆn l—&uart1-ctsˆ
nuart1-rtsˆluart2uart2-xfer ˆnl—'uart3uart3-xfer ˆnl—(uart3-ctsˆ nuart3-rtsˆ
luart4uart4-xfer ˆnl—)uart4-ctsˆnuart4-rtsˆ
ltsadcotp-pinˆ
l—/otp-outˆ
l—0pwm0pwm0-pinˆl—@pwm1pwm1-pinˆl—Apwm2pwm2-pinˆl—Bpwm3pwm3-pinˆl—Cgmacrgmii-pinsðˆllllpppplll ppll—5rmii-pins ˆllllllllllspdifspdif-txˆl—Spcfg-output-highÙ—qact8846pmic-vselˆm—=pwr-holdˆq—>buttonspwrbtnˆn—ririr-intˆn—tpmicpmic-intˆn—<�usbhost-vbus-drvˆl—uotg-vbus-drvˆl—vmemory@0#memory/€external-gmac-clockfixed-clockÆsY@ Öext_gmacé—4gpio-keys
gpio-keyså¹defaultÇrkey-powerð;ötGPIO Key Power&dir-receivergpio-ir-receiverðs¹defaultÇtvcc-host-regulatorregulator-fixed8†;¹defaultÇu jvcc_hostÚîvcc-otg-regulatorregulator-fixed8†;¹defaultÇvjvcc_otgÚîsdmmc-regulatorregulator-fixed
jsdmmc-supply•2Z 2Z †sK† w—sys-regulatorregulator-fixedjsys-supply•LK@LK@Úî—: #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supply#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplysystem-power-controller#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervalenable-active-highstartup-delay-us