Ð þíø 8î$( çíìDcompulab,omap3-sbc-t3517compulab,omap3-cm-t3517ti,am3517ti,omap3 +!7CompuLab SBC-T3517 with CM-T3517chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@4809e000{/ocp@68000000/can@5c050000 /ocp@68000000/ethernet@5c000000ˆ/dvi-connector‘/svideo-connectorcpus+cpu@0arm,cortex-a8šcpu¦ª±cpu½“àËpmu@54000000arm,cortex-a8-pmu¦T€ßêdebugsssocti,omap-inframpu ti,omap3-mpuêmpuiva ti,iva2.2êiva ôdisableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus¦hß +ûêl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ ûHscm@2000ti,omap3-scmsimple-bus¦ + û pinmux@30 ti,omap3-padconfpinctrl-single¦08+"7Uÿrdefault€uart3-pinsŠnpžÐmmc1-pins0ŠžØgreen-led-pinsŠ²žödss-dpi-common-pins°Š¤¦¨ª¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚžïdss-dpi-cm-t35x-pins0Š¬®°²´¶žðads7846-pinsŠŠžÔmcspi1-pins Š˜šœžžÓi2c1-pinsŠŠŒžÑmcbsp2-pins Š žáhsusb1-phy-reset-pinsŠHžùhsusb2-phy-reset-pinsŠJžûotg-drv-vbus-pinsŠàžómmc2-pins0Š(*,.02žÜwl12xx-core-pinsŠˆFžþusb-hub-pinsŠTžsmsc2-pinsŠ†¢žëtfp410-pinsŠ„ži2c3-pinsŠ’”žÒsb-t35-audio-amp-pinsŠ˜žmmc1-aux-pinsŠDžÙsb-t35-usb-hub-pinsŠ¼žscm_conf@270sysconsimple-bus¦p0+ ûp0žpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap¦°¦pbias_mmc_omap2430­pbias_mmc_omap2430¼w@Ô-ÆÀž×clocks+clock@68 ti,clksel¦hì+clock-mcbsp5-mux-fck@4¦ìti,composite-mux-clockùmcbsp5_mux_fckªž clock-mcbsp3-mux-fck@0¦ìti,composite-mux-clockùmcbsp3_mux_fckª žclock-mcbsp4-mux-fck@2¦ìti,composite-mux-clockùmcbsp4_mux_fckª žmcbsp5_fckìti,composite-clockª žäclock@4 ti,clksel¦ì+clock-mcbsp1-mux-fck@2¦ìti,composite-mux-clockùmcbsp1_mux_fckªž clock-mcbsp2-mux-fck@6¦ìti,composite-mux-clockùmcbsp2_mux_fckª žmcbsp1_fckìti,composite-clockª žßmcbsp2_fckìti,composite-clockªžàmcbsp3_fckìti,composite-clockªžâmcbsp4_fckìti,composite-clockªžãemac_ick@32cìti,am35xx-gate-clockª¦, žzemac_fck@32cìti,gate-clockª¦, žôvpfe_ick@32cìti,am35xx-gate-clockª¦, ž{vpfe_fck@32cìti,gate-clockª¦, hsotgusb_ick_am35xx@32cìti,am35xx-gate-clockª¦, ž|hsotgusb_fck_am35xx@32cìti,gate-clockª¦, ž}hecc_ck@32cìti,am35xx-gate-clockª¦, ž~clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single¦ \+"7Uÿwl12xx-wkup-pinsŠžýprm@48306000 ti,omap3-prm¦H0`@ß clocks+virt_16_8m_ckì fixed-clockYžosc_sys_ck@d40ì ti,mux-clockª¦ @žsys_ck@1270ìti,divider-clockª )¦p4žsys_clkout1@d70ìti,gate-clockª¦ p dpll3_x2_ckìfixed-factor-clockªKVdpll3_m2x2_ckìfixed-factor-clockª KVž"dpll4_x2_ckìfixed-factor-clockª!KVcorex2_fckìfixed-factor-clockª"KVž#wkup_l4_ickìfixed-factor-clockªKVžXcorex2_d3_fckìfixed-factor-clockª#KVžtcorex2_d5_fckìfixed-factor-clockª#KVžuclockdomainscm@48004000 ti,omap3-cm¦H@@clocks+dummy_apb_pclkì fixed-clockomap_32k_fckì fixed-clock€žHvirt_12m_ckì fixed-clock·žvirt_13m_ckì fixed-clockÆ]@žvirt_19200000_ckì fixed-clock$øžvirt_26000000_ckì fixed-clockŒº€žvirt_38_4m_ckì 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ì+clock-gpt1-gate-fck@0¦ìti,composite-gate-clockùgpt1_gate_fckªžVclock-gpio1-dbck@3¦ìti,gate-clock ùgpio1_dbckªUž™clock-wdt2-fck@5¦ìti,wait-gate-clock ùwdt2_fckªUžšgpt1_fckìti,composite-clockªVWžåwkup_32k_fckìfixed-factor-clockªHKVžUclock@c10 ti,clksel¦ ì+clock-wdt2-ick@5¦ìti,omap3-interface-clock ùwdt2_ickªXž›clock-wdt1-ick@4¦ìti,omap3-interface-clock ùwdt1_ickªXžœclock-gpio1-ick@3¦ìti,omap3-interface-clock ùgpio1_ickªXžclock-omap-32ksync-ick@2¦ìti,omap3-interface-clockùomap_32ksync_ickªXžžclock-gpt12-ick@1¦ìti,omap3-interface-clock ùgpt12_ickªXžŸclock-gpt1-ick@0¦ìti,omap3-interface-clock ùgpt1_ickªXž per_96m_fckìfixed-factor-clockª2KVž per_48m_fckìfixed-factor-clockª9KVžYclock@1000 ti,clksel¦ì+clock-uart3-fck@11¦ ìti,wait-gate-clock ùuart3_fckªYžclock-gpt2-gate-fck@3¦ìti,composite-gate-clockùgpt2_gate_fckªž[clock-gpt3-gate-fck@4¦ìti,composite-gate-clockùgpt3_gate_fckªž]clock-gpt4-gate-fck@5¦ìti,composite-gate-clockùgpt4_gate_fckªž_clock-gpt5-gate-fck@6¦ìti,composite-gate-clockùgpt5_gate_fckªžaclock-gpt6-gate-fck@7¦ìti,composite-gate-clockùgpt6_gate_fckªžcclock-gpt7-gate-fck@8¦ìti,composite-gate-clockùgpt7_gate_fckªžeclock-gpt8-gate-fck@9¦ ìti,composite-gate-clockùgpt8_gate_fckªžgclock-gpt9-gate-fck@10¦ ìti,composite-gate-clockùgpt9_gate_fckªžiclock-gpio6-dbck@17¦ìti,gate-clock ùgpio6_dbckªZž€clock-gpio5-dbck@16¦ìti,gate-clock ùgpio5_dbckªZžclock-gpio4-dbck@15¦ìti,gate-clock ùgpio4_dbckªZž‚clock-gpio3-dbck@14¦ìti,gate-clock ùgpio3_dbckªZžƒclock-gpio2-dbck@13¦ ìti,gate-clock ùgpio2_dbckªZž„clock-wdt3-fck@12¦ ìti,wait-gate-clock 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3canethernetdisplay0display1device_typeregclocksclock-namesclock-latencyoperating-points-v2interruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namespagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplywp-gpioscd-gpiosvqmmc-supplynon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsremote-endpointti,channelsdata-linesti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqopp-hzopp-microvoltopp-supported-hwopp-suspendlinux,default-triggerstartup-delay-us#phy-cellsreset-gpiosenable-active-highpowerdown-gpiosregulator-always-on