Ð
þíkú8fp(Šf8 ,Olimex A20-SOM204-EVB12olimex,a20-olimex-som204-evballwinner,sun7i-a20aliases=/soc/ethernet@1c50000G/soc/serial@1c28000O/soc/serial@1c29000W/soc/serial@1c29c00_/soc/spi@1c06000d/soc/spi@1c17000i/soc/mmc@1c12000/wifi@1chosen szserial0:115200n8framebuffer-lcd0-hdmi02allwinner,simple-framebuffersimple-framebuffer†de_be0-lcd0-hdmi8™8<�>›Œ¤ disabledframebuffer-lcd002allwinner,simple-framebuffersimple-framebuffer†de_be0-lcd0(™8>•Œ disabledframebuffer-lcd0-tve002allwinner,simple-framebuffersimple-framebuffer†de_be0-lcd0-tve08™68>›‡Œ disabledcpus cpu@02arm,cortex-a7§cpu³™·¹°8Ŧ\À
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/Ö
ü€O€€ÈàÂÀB@2€B@Öåðcpu@12arm,cortex-a7§cpu³™·¹°8Ŧ\À
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/Ö
ü€O€€ÈàÂÀB@2€B@Öðthermal-zonescpu-thermaløúècooling-mapsmap0,1ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtripscpu-alert0@$øLЮpassiveðcpu-crit@† LÐ ®criticalreserved-memory sdefault-pool2shared-dma-poolW\@irtimer2arm,armv7-timer0„
pmu2arm,cortex-a7-pmu„xyclocks sclk-24M2fixed-clockœn6¬osc24Mð)clk-32k2fixed-clockœ€¬osc32kð*clk-mii-phy-tx2fixed-clockœ}x@¬mii_phy_txðclk-gmac-int-tx2fixed-clockœsY@¬gmac_int_txð clk@1c201642allwinner,sun7i-a20-gmac-clk³Âd™ ¬gmac_txð7display-engine#2allwinner,sun7i-a20-display-engine¿
okaysoc2simple-bus ssystem-control@1c00000F2allwinner,sun7i-a20-system-controlallwinner,sun4i-a10-system-control³À0 ssram@0
2mmio-sram³À sÀsram-section@8000>2allwinner,sun7i-a20-sram-a3-a4allwinner,sun4i-a10-sram-a3-a4³€@ disabledðsram@10000
2mmio-sram³ ssram-section@062allwinner,sun7i-a20-sram-dallwinner,sun4i-a10-sram-d³ okayðsram@1d00000
2mmio-sram³Ð
sÐ
sram-section@082allwinner,sun7i-a20-sram-c1allwinner,sun4i-a10-sram-c1³ðinterrupt-controller@1c000302allwinner,sun7i-a20-sc-nmiÓè³À0„ð2dma-controller@1c020002allwinner,sun4i-a10-dma³À „™ ùðnand-controller@1c030002allwinner,sun4i-a10-nand³À0„%™'`ahbmodrxtx disabled spi@1c050002allwinner,sun4i-a10-spi³ÀP„
™,pahbmodrxtx disabled spi@1c060002allwinner,sun4i-a10-spi³À`„™-qahbmod rxtx okay &default4
csi@1c090002allwinner,sun7i-a20-csi0³À„*™:—ƒbusispram> disabledethernet@1c0b0002allwinner,sun4i-a10-emac³À°„7™*E disabledmdio@1c0b0802allwinner,sun4i-a10-mdio³À°€ disabled lcd-controller@1c0c00032allwinner,sun7i-a20-tcon0allwinner,sun7i-a20-tcon³ÀÀ„,> Tlcdlvds™8•›ahbtcon-ch0tcon-ch1¬tcon0-pixel-clockports port@0 ³endpoint@0³`ðDendpoint@1³`ð@port@1 ³endpoint@1³`pð#lcd-controller@1c0d00032allwinner,sun7i-a20-tcon1allwinner,sun7i-a20-tcon³ÀЄ->
Tlcd™9–ahbtcon-ch0tcon-ch1¬tcon1-pixel-clockports port@0 ³endpoint@0³`ðEendpoint@1³`ðAport@1 ³endpoint@1³`pð$video-codec@1c0e000!2allwinner,sun7i-a20-video-engine³Àà™4¡‚ahbmodram>„5Emmc@1c0f0002allwinner,sun7i-a20-mmc³Àð ™"bcdahbmmcoutputsample„ &default4 okay ‡“mmc@1c100002allwinner,sun7i-a20-mmc³Á ™#efgahbmmcoutputsample„! disabled mmc@1c110002allwinner,sun7i-a20-mmc³Á ™$hijahbmmcoutputsample„"&default4 disabled mmc@1c120002allwinner,sun7i-a20-mmc³Á ™%klmahbmmcoutputsample„#&default4 okay ‡¦“±wifi@1³usb@1c130002allwinner,sun4i-a10-musb³Á0™„&¿mcÏÔusbÞEåotg okayphy@1c13400í2allwinner,sun7i-a20-usb-phy³Á4ÁHÁÈøphy_ctrlpmu1pmu2™}usb_phy>!Tusb0_resetusb1_resetusb2_reset okay(? P!a"ðusb@1c14000&2allwinner,sun7i-a20-ehcigeneric-ehci³Á@„'™ÏÔusb okayusb@1c14400&2allwinner,sun7i-a20-ohcigeneric-ohci³ÁD„@™{ÏÔusb okaycrypto-engine@1c1500062allwinner,sun7i-a20-cryptoallwinner,sun4i-a10-crypto³ÁP„V™oahbmodhdmi@1c1600032allwinner,sun7i-a20-hdmiallwinner,sun5i-a10s-hdmi³Á`„: ™<�¤ ahbmodpll-0pll-1$ddc-txddc-rxaudio-tx okayports port@0 ³endpoint@0³`#ðendpoint@1³`$ðport@1³endpoint`%ðFspi@1c170002allwinner,sun4i-a10-spi³Áp„™.rahbmodrxtx okay &default4&'sata@1c180002allwinner,sun4i-a10-ahci³Á€„8™1z okayr(usb@1c1c000&2allwinner,sun7i-a20-ehcigeneric-ehci³ÁÀ„(™ÏÔusb okayusb@1c1c400&2allwinner,sun7i-a20-ohcigeneric-ohci³ÁÄ„A™|ÏÔusb okaycsi@1c1d00022allwinner,sun7i-a20-csi1allwinner,sun4i-a10-csi1³ÁЄ+™;„busram> disabledspi@1c1f0002allwinner,sun4i-a10-spi³Áð„2™/ahbmodrxtx disabled clock@1c200002allwinner,sun7i-a20-ccu³Â™)*
hosclosc€ðpinctrl@1c208002allwinner,sun7i-a20-pinctrl³Â„™J)*apbhoscloscÓèðcan-ph-pins
©PH20PH21®canð6gmac-rgmii-pinsB©PA0PA1PA2PA3PA4PA5PA6PA7PA8PA10PA11PA12PA13PA15PA16®gmac·(ð8i2c0-pins©PB0PB1®i2c0ð1i2c1-pins
©PB18PB19®i2c1ð3i2c2-pins
©PB20PB21®i2c2ð4i2c3-pins©PI0PI1®i2c3ð5ir0-rx-pin©PB4®ir0ð+mmc0-pins©PF0PF1PF2PF3PF4PF5®mmc0·Æðmmc2-pins©PC6PC7PC8PC9PC10PC11®mmc2·Æðmmc3-pins©PI4PI5PI6PI7PI8PI9®mmc3·Æðspi1-pi-pins©PI17PI18PI19®spi1ð
spi1-cs0-pi-pin©PI16®spi1ðspi2-pc-pins©PC20PC21PC22®spi2ð&spi2-cs0-pc-pin©PC19®spi2ð'uart0-pb-pins
©PB22PB23®uart0ð,uart3-pg-pins©PG6PG7®uart3ð-uart4-pg-pins
©PG10PG11®uart4ð/uart7-pi-pins
©PI20PI21®uart7ð0uart3-rts-pin©PG8®uart3ð.timer@1c20c002allwinner,sun4i-a10-timer³ÂH„CD™)watchdog@1c20c902allwinner,sun4i-a10-wdt³Â„™)rtc@1c20d002allwinner,sun7i-a20-rtc³Â
„pwm@1c20e002allwinner,sun7i-a20-pwm³Â™)Ó disabledspdif@1c21000Þ2allwinner,sun4i-a10-spdif³Â„
™Fx
apbspdifrxtx disabledir@1c218002allwinner,sun4i-a10-ir™Ktapbir„³Â@ okay&default4+ir@1c21c002allwinner,sun4i-a10-ir™Luapbir„³Â@ disabledi2s@1c22000Þ2allwinner,sun4i-a10-i2s³Â „W™I€apbmodrxtx disabledi2s@1c22400Þ2allwinner,sun4i-a10-i2s³Â$„™Gvapbmodrxtx disabledlradc@1c228002allwinner,sun4i-a10-lradc-keys³Â(„ disabledcodec@1c22c00Þ2allwinner,sun7i-a20-codec³Â,@„™E
apbcodecrxtx okayeeprom@1c238002allwinner,sun7i-a20-sid³Â8i2s@1c24400Þ2allwinner,sun4i-a10-i2s³ÂD„Z™Mapbmodrxtx disabledrtp@1c250002allwinner,sun5i-a13-ts³ÂP„ïðserial@1c280002snps,dw-apb-uart³Â€„™X okay&default4,serial@1c284002snps,dw-apb-uart³Â„„™Y disabledserial@1c288002snps,dw-apb-uart³Âˆ„™Z disabledserial@1c28c002snps,dw-apb-uart³ÂŒ„™[ okay&default4-.serial@1c290002snps,dw-apb-uart³Â„™\ okay&default4/serial@1c294002snps,dw-apb-uart³Â”„™] disabledserial@1c298002snps,dw-apb-uart³Â˜„™^ disabledserial@1c29c002snps,dw-apb-uart³Âœ„™_ okay&default40ps2@1c2a0002allwinner,sun4i-a10-ps2³Â „>™U disabledps2@1c2a4002allwinner,sun4i-a10-ps2³Â¤„?™V disabledi2c@1c2ac0002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c³Â¬„™O&default41 okay pmic@34³42„2x-powers,axp209Óèac-power 2x-powers,axp202-ac-power-supply okayadc2x-powers,axp209-adcðGgpio2x-powers,axp209-gpiobattery-power%2x-powers,axp209-battery-power-supply okayregulators.Üdcdc2Avdd-cpuPdB@|\Àðdcdc3Avdd-int-dllPdB@|\Àldo1PdÖ |Ö Avdd-rtcldo2AavccPd-ÆÀ|-ÆÀldo3Aldo3ldo4Avcc-pgd2Z |2Z ldo5Aldo5 disabledusb-power!2x-powers,axp202-usb-power-supply okayði2c@1c2b00002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c³Â°„™P&default43 okay eeprom@502atmel,24c16³P”i2c@1c2b40002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c³Â´„ ™Q&default44 okay i2c@1c2b80002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c³Â¸„X™R&default45 disabled can@1c2bc0002allwinner,sun7i-a20-canallwinner,sun4i-a10-can³Â¼„™S okay&default46i2c@1c2c00002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c³ÂÀ„Y™W disabled gpu@1c40000&2allwinner,sun7i-a20-maliarm,mali-400³ÄT„EFGHJKI#¿gpgpmmupp0ppmmu0pp1ppmmu1pmu™D¥ buscore>¥ã`ethernet@1c500002allwinner,sun7i-a20-gmac³Å„U¿macirq™B7stmmacethallwinner_gmac_txÂËÜ okay&default48ó9þrgmiimdio2snps,dwmac-mdio ethernet-phy@3³'.B@ð9hstimer@1c600002allwinner,sun7i-a20-hstimer³Æ0„QRST™3interrupt-controller@1c810002arm,gic-400 ³ÈÈ È@ È` Óè„ ðdisplay-frontend@1e00000%2allwinner,sun7i-a20-display-frontend³à„/™@’‹ahbmodram>ð
ports port@1 ³endpoint@0³`:ðBendpoint@1³`;ð>display-frontend@1e20000%2allwinner,sun7i-a20-display-frontend³â„0™A“Šahbmodram>ðports port@1 ³endpoint@0³`<�ðCendpoint@1³`=ð?display-backend@1e40000$2allwinner,sun7i-a20-display-backend³ä„0™?‘ahbmodram>ports port@0 ³endpoint@0³`>ð;endpoint@1³`?ð=port@1 ³endpoint@0³`@ðendpoint@1³`Aðdisplay-backend@1e60000$2allwinner,sun7i-a20-display-backend³æ„/™>Œahbmodram>ports port@0 ³endpoint@0³`Bð:endpoint@1³`Cð<�port@1 ³endpoint@0³`Dðendpoint@1³`Eðahci-5v2regulator-fixedAahci-5vdLK@|LK@@Re okayð(usb0-vbus2regulator-fixed
Ausb0-vbusdLK@|LK@Re okayð usb1-vbus2regulator-fixed
Ausb1-vbusdLK@|LK@@Re okayð!usb2-vbus2regulator-fixed
Ausb2-vbusdLK@|LK@@Re okayð"vcc3v02regulator-fixedAvcc3v0d-ÆÀ|-ÆÀvcc3v32regulator-fixedAvcc3v3d2Z |2Z ðvcc5v02regulator-fixedAvcc5v0dLK@|LK@hdmi-connector2hdmi-connector®aportendpoint`Fð%leds
2gpio-ledsled-0ja20-som204-evb:green:stat ponled-1ja20-som204-evb:green:led1
ponled-2ja20-som204-evb:yellow:led2 ponpwrseq-02mmc-pwrseq-simple ðpmic-temp
2iio-hwmon~G interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0serial0serial1serial2spi0spi1ethernet1rangesstdout-pathallwinner,pipelineclocksstatusdevice_typeregclock-latencyoperating-points#cooling-cellscpu-supplyphandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresissizealloc-rangesreusablelinux,cma-defaultinterrupts#clock-cellsclock-frequencyclock-output-namesallwinner,pipelinesinterrupt-controller#interrupt-cells#dma-cellsclock-namesdmasdma-namesnum-cspinctrl-namespinctrl-0resetsallwinner,sramreset-namesremote-endpointallwinner,tcon-channelvmmc-supplybus-widthcd-gpiosmmc-pwrseqnon-removableinterrupt-namesphysphy-namesextcondr_mode#phy-cellsreg-namesusb0_id_det-gpiosusb0_vbus_det-gpiosusb0_vbus_power-supplyusb0_vbus-supplyusb1_vbus-supplyusb2_vbus-supplytarget-supply#reset-cellsgpio-controller#gpio-cellspinsfunctiondrive-strengthbias-pull-up#pwm-cells#sound-dai-cells#thermal-sensor-cellsreg-shiftreg-io-width#io-channel-cellsx-powers,dcdc-freqregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltpagesizeassigned-clocksassigned-clock-ratessnps,pblsnps,fixed-burstsnps,force_sf_dma_modephy-handlephy-modephy-supplyreset-gpiosreset-assert-usreset-deassert-usregulator-boot-onenable-active-highgpiolabeldefault-stateio-channels