Ð
þíe8a0(]`ø ,Yones TopTech BS1078 v2 Tablet-2yones-toptech,bs1078-v2allwinner,sun6i-a31saliases=/soc/ethernet@1c30000G/soc/serial@1c28000O/soc/i2c@1c2b000T/soc/i2c@1c2b400chosen Y`serial0:115200n8framebuffer-lcd0-hdmi02allwinner,simple-framebuffersimple-framebufferlde_be0-lcd0-hdmi@3/2w’zŠ †disabledframebuffer-lcd002allwinner,simple-framebuffersimple-framebufferlde_be0-lcd003/w’z †disabledtimer2arm,armv7-timer0
˜n6¨cpusÌallwinner,sun6i-a31 cpu@02arm,cortex-a7Úcpuæê¹° øa€O€
/O€
ü€ÈàSB@ cpu@12arm,cortex-a7Úcpuæê¹° øa€O€
/O€
ü€ÈàSB@ cpu@22arm,cortex-a7Úcpuæê¹° øa€O€
/O€
ü€ÈàSB@ cpu@32arm,cortex-a7Úcpuæê¹° øa€O€
/O€
ü€ÈàSB@ thermal-zonescpu-thermal ú6èDcooling-mapsmap0T0Yÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtripscpu-alert0hptÐápassivecpu-crith† tÐ ácriticalpmu2arm,cortex-a7-pmu0xyz{clocks Yclk-24M2fixed-clock˜n6ŒÃP›osc24Mclk-32k2fixed-clock˜€ŒÃP›ext_osc32k5clk-mii-phy-tx2fixed-clock˜}x@›mii_phy_tx clk-gmac-int-tx2fixed-clock˜sY@›gmac_int_tx
clk@1c200d02allwinner,sun7i-a20-gmac-clkæÂÐ
›gmac_tx$display-engine$2allwinner,sun6i-a31s-display-engine® †disabledsoc2simple-bus Ydma-controller@1c020002allwinner,sun6i-a31-dmaæÀ 2ÂÉ
lcd-controller@1c0c0002allwinner,sun6i-a31s-tconæÀÀVÔ
Â) Ùlcdlvds /åahbtcon-ch0tcon-ch1lvds-alt›tcon0-pixel-clockports port@0 æendpoint@0æñ3endpoint@1æñ-port@1 æendpoint@1æñlcd-controller@1c0d0002allwinner,sun6i-a31-tconæÀÐWÔ
Â) Ùlcdlvds 0€‚åahbtcon-ch0tcon-ch1lvds-alt›tcon1-pixel-clockports port@0 æendpoint@0æñ4endpoint@1æñ.port@1 æendpoint@1æñmmc@1c0f0002allwinner,sun7i-a20-mmcæÀð OQPåahbmmcoutputsampleÂÙahb<�default&†okay 0<�Fmmc@1c100002allwinner,sun7i-a20-mmcæÁ RTSåahbmmcoutputsampleÂÙahb=default& †disabled mmc@1c110002allwinner,sun7i-a20-mmcæÁ UWVåahbmmcoutputsampleÂÙahb> †disabled mmc@1c120002allwinner,sun7i-a20-mmcæÁ XZYåahbmmcoutputsample Ùahb? †disabled hdmi@1c160002allwinner,sun6i-a31-hdmiæÁ`X(2Š‹
åahbmodddcpll-0pll-1ÂOddc-txddc-rxaudio-txÔ
†disabledports port@0 æendpoint@0æñendpoint@1æñport@1æusb@1c190002allwinner,sun6i-a31-musbæÁ(ÂGYmcinusbxotg †disabledphy@1c194002allwinner,sun6i-a31-usb-phyæÁ”Á¨Á¸‡phy_ctrlpmu1pmu2defåusb0_phyusb1_phyusb2_phyÂ!Ùusb0_resetusb1_resetusb2_reset†okay‘œusb@1c1a000&2allwinner,sun6i-a31-ehcigeneric-ehciæÁ H)Âinusb†okayusb@1c1a400&2allwinner,sun6i-a31-ohcigeneric-ohciæÁ¤I+gÂinusb†okayusb@1c1b000&2allwinner,sun6i-a31-ehcigeneric-ehciæÁ°J*Âinusb†okayusb@1c1b400&2allwinner,sun6i-a31-ohcigeneric-ohciæÁ´K,hÂinusb†okayusb@1c1c400&2allwinner,sun6i-a31-ohcigeneric-ohciæÁÄM-i †disabledclock@1c200002allwinner,sun6i-a31-ccuæÂ
åhosclosc¾pinctrl@1c208002allwinner,sun6i-a31s-pinctrlæÂ0@åapbhoscloscËÛðgmac-gmii-pins‚
PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27gmacgmac-mii-pinsT
PA0PA1PA2PA3PA8PA9PA11PA12PA13PA14PA19PA20PA21PA22PA23PA24PA26PA27gmacgmac-rgmii-pinsF
PA0PA1PA2PA3PA9PA10PA11PA12PA13PA14PA19PA20PA25PA26PA27gmac(i2c0-pins
PH14PH15i2c0!i2c1-pins
PH16PH17i2c1"i2c2-pins
PH18PH19i2c2#lcd0-rgb888-pins‚
PD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27lcd0mmc0-pins
PF0PF1PF2PF3PF4PF5mmc0*mmc1-pins
PG0PG1PG2PG3PG4PG5mmc1*mmc2-4bit-pins
PC6PC7PC8PC9PC10PC11mmc2*mmc2-8bit-emmc-pins3
PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24mmc2*mmc3-8bit-emmc-pins3
PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24mmc3(*spdif-tx-pin
PH28spdifuart0-ph-pins
PH20PH21uart0 timer@1c20c002allwinner,sun4i-a10-timeræ Hwatchdog@1c20ca02allwinner,sun6i-a31-wdtæ spdif@1c2100072allwinner,sun6i-a31-spdifæÂ>cÂ+
åapbspdifÔ
Orxtx †disabledi2s@1c2200072allwinner,sun6i-a31-i2sæÂ
AaÂ-åapbmodÔ
Orxtx †disabledi2s@1c2240072allwinner,sun6i-a31-i2sæÂ$BbÂ.åapbmodÔ
Orxtx †disabledlradc@1c228002allwinner,sun4i-a10-lradc-keysæÂ( †disabledrtp@1c250002allwinner,sun6i-a31-tsæÂPHserial@1c280002snps,dw-apb-uartæ€^hGÂ3Ô
Otxrx†okaydefault& serial@1c284002snps,dw-apb-uartæ„^hHÂ4Ô
Otxrx †disabledserial@1c288002snps,dw-apb-uartæˆ^hIÂ5Ô
Otxrx †disabledserial@1c28c002snps,dw-apb-uartæÂŒ^hJÂ6Ô
Otxrx †disabledserial@1c290002snps,dw-apb-uartæÂ^hKÂ7Ô
Otxrx †disabledserial@1c294002snps,dw-apb-uartæ”^hLÂ8Ô
Otxrx †disabledi2c@1c2ac002allwinner,sun6i-a31-i2cæ¬CÂ/default&! †disabled i2c@1c2b0002allwinner,sun6i-a31-i2cæ°DÂ0default&"†okay i2c@1c2b4002allwinner,sun6i-a31-i2cæ´EÂ1default&#†okay i2c@1c2b8002allwinner,sun6i-a31-i2cæ¸ FÂ2 †disabled ethernet@1c300002allwinner,sun7i-a20-gmacæÃTRYmacirq!$åstmmacethallwinner_gmac_txÂ
Ùstmmacethu~ †disabledmdio2snps,dwmac-mdio crypto-engine@1c1500062allwinner,sun6i-a31-cryptoallwinner,sun4i-a10-cryptoæÁPP\åahbmodÂÙahbcodec@1c22c0072allwinner,sun6i-a31-codecæÂ,=‡
åapbcodecÂ*Ô
Orxtx †disabledtimer@1c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimeræÆ03456#Âspi@1c680002allwinner,sun6i-a31-spiæÆ€A$]åahbmodÔ
Orxtx †disabled spi@1c690002allwinner,sun6i-a31-spiæÆB%^åahbmodÔ
Orxtx †disabled spi@1c6a0002allwinner,sun6i-a31-spiæÆ C&_åahbmodÔ
Orxtx †disabled spi@1c6b0002allwinner,sun6i-a31-spiæÆ°D'`åahbmodÔ
Orxtx †disabled interrupt-controller@1c810002arm,gic-400 æÈÈ È@ È` Ûð display-frontend@1e00000%2allwinner,sun6i-a31-display-frontendæà]5|uåahbmodramÂ!ports port@1 æendpoint@0æñ%/endpoint@1æñ&)display-frontend@1e20000%2allwinner,sun6i-a31-display-frontendæâ^6}våahbmodramÂ"ports port@1 æendpoint@0æñ'0endpoint@1æñ(*display-backend@1e40000$2allwinner,sun6i-a31-display-backendæä`4{xåahbmodram ports port@0 æendpoint@0æñ)&endpoint@1æñ*(port@1 æendpoint@1æñ+,drc@1e500002allwinner,sun6i-a31-drcæå[<�“råahbmodramÂ(ports port@0 æendpoint@1æñ,+port@1 æendpoint@0æñ-endpoint@1æñ.display-backend@1e60000$2allwinner,sun6i-a31-display-backendææ_3zwåahbmodramÂports port@0 æendpoint@0æñ/%endpoint@1æñ0'port@1æendpointñ12drc@1e700002allwinner,sun6i-a31-drcæç[;’qåahbmodramÂ'ports port@0æendpointñ21port@1 æendpoint@0æñ3endpoint@1æñ4rtc@1f000002allwinner,sun6i-a31-rtcæðT()5›osc32kinterrupt-controller@1f00c002allwinner,sun6i-a31-r-intcÛðæð prcm@1f014002allwinner,sun6i-a31-prcmæðar100-clk2allwinner,sun6i-a31-ar100-clk
›ar1006ahb0-clk2fixed-factor-clock¦°6›ahb07apb0-clk2allwinner,sun6i-a31-apb0-clk7›apb08apb0-gates-clk#2allwinner,sun6i-a31-apb0-gates-clk8D›apb0_pioapb0_irapb0_timerapb0_p2wiapb0_uartapb0_1wireapb0_i2c9ir-clk2allwinner,sun4i-a10-mod0-clk›ir:apb0-rst 2allwinner,sun6i-a31-clock-reset¾;cpucfg@1f01c002allwinner,sun6i-a31-cpuconfigæðir@1f020002allwinner,sun6i-a31-ir9:åapbirÂ;%æð @ †disabledpinctrl@1f02c002allwinner,sun6i-a31-r-pinctrlæð,-.9åapbhoscloscËÛðs-ir-rx-pin
PL4s_irs-p2wi-pins
PL0PL1s_p2wi<�i2c@1f034002allwinner,sun6i-a31-p2wiæð4'9˜† Â;default&<�†okay pmic@682x-powers,axp221æh Ûðac-power 2x-powers,axp221-ac-power-supply †disabledadc2x-powers,axp221-adc»battery-power%2x-powers,axp221-battery-power-supply †disabledgpio2x-powers,axp221-gpioËregulators͸dcdc1àvcc-3v0ï-ÆÀ-ÆÀdcdc2àvdd-gpu
®`$@dcdc3àvdd-cpuï
®`$@dcdc4àvdd-sys-dllï
®`$@dcdc5 àvcc-dramïã`ã`dc1sw
àvcc-lcd-usb2dc5ldo àvdd-cpus
®`$@aldo1àaldo1aldo2àaldo2aldo3àavccï)2à2Z dldo1 àvcc-wifi2Z 2Z dldo2àdldo2dldo3
àvddio-csi*¹€*¹€dldo4àdldo4eldo1àeldo1eldo2àeldo2eldo3àeldo3ldo_io0àldo_io0 †disabledldo_io1àldo_io1 †disabledrtc_ldoï-ÆÀ-ÆÀàrtc_ldodrivevbus
àdrivevbus †disabledusb-power!2x-powers,axp221-usb-power-supply †disabledahci-5v2regulator-fixedàahci-5vLK@LK@3EX †disabledusb0-vbus2regulator-fixed
àusb0-vbusLK@LK@EX †disabledusb1-vbus2regulator-fixed
àusb1-vbusLK@LK@3EX †disabledusb2-vbus2regulator-fixed
àusb2-vbusLK@LK@3EX †disabledvcc3v02regulator-fixedàvcc3v0-ÆÀ-ÆÀvcc3v32regulator-fixedàvcc3v32Z 2Z vcc5v02regulator-fixedàvcc5v0LK@LK@ interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0serial0i2c1i2c2rangesstdout-pathallwinner,pipelineclocksstatusinterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-methoddevice_typeregclock-latencyoperating-points#cooling-cellsphandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresis#clock-cellsclock-accuracyclock-output-namesallwinner,pipelinesresets#dma-cellsdmasreset-namesclock-namesremote-endpointallwinner,tcon-channelpinctrl-namespinctrl-0vmmc-supplybus-widthcd-gpiosdma-namesinterrupt-namesphysphy-namesextcondr_modereg-names#phy-cellsusb1_vbus-supplyusb2_vbus-supply#reset-cellsgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellspinsfunctiondrive-strengthbias-pull-up#sound-dai-cells#thermal-sensor-cellsreg-shiftreg-io-widthsnps,pblsnps,fixed-burstsnps,force_sf_dma_modeclock-divclock-mult#io-channel-cellsx-powers,dcdc-freqregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-highgpio