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Èâ® ! ïi2cpclkûdefault okayæ€pmic@20rockchip,rk809œ &È ürk808-clkout1rk808-clkout2ûdefault 4BNZfr~Š– ¢ÀOregulatorsDCDC_REG1 ®vdd_npu_vepu½Ñãú ë~ð*qregulator-state-mem?DCDC_REG2®vdd_arm½Ñãú ™p*qÀregulator-state-mem?DCDC_REG3®vcc_ddr½Ñãregulator-state-memXDCDC_REG4 ®vcc3v3_sys½Ñãú2Z 2Z À regulator-state-memXp2Z DCDC_REG5 ®vcc_buck5½Ñú!‘À!‘ÀÀregulator-state-memXp!‘ÀLDO_REG1®vcc_0v8½Ñú 5 5regulator-state-mem?LDO_REG2 ®vcc1v8_pmu½Ñúw@w@À regulator-state-memXpw@LDO_REG3 ®vcc0v8_pmu½Ñú 5 5regulator-state-memXp 5LDO_REG4®vcc_1v8½Ñúw@w@À regulator-state-memXpw@LDO_REG5 ®vcc_dovdd½Ñúw@w@Àregulator-state-mem?LDO_REG6 ®vcc_dvddúO€O€regulator-state-mem?LDO_REG7 ®vcc_avddú*¹€*¹€regulator-state-mem?LDO_REG8 ®vccio_sd½Ñúw@2Z À regulator-state-mem?LDO_REG9 ®vcc3v3_sd½Ñú2Z 2Z À regulator-state-mem?SWITCH_REG1®vcc_5v0SWITCH_REG2®vcc_3v3½ÑÀ6i2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2cœÿ@ Èâ® " ïi2cpclkûdefault okayæ€rtc@51 nxp,pcf8563œQ&Èüxin32kserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uartœÿA È æn6®  ïbaudclkapb_pclkŒ‘txrxûdefault ›¥ disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwmœÿC  ïpwmpclk®#ûdefault !² disabledclock-controller@ff480000rockchip,rv1126-pmucruœÿHâ"½Àclock-controller@ff490000rockchip,rv1126-cruœÿI®#ïxin24mâ"½Àdma-controller@ff4e0000arm,pl330arm,primecellœÿN@ÈÊÕ®¡ ïapb_pclkÀpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwmœÿU0 ïpwmpclk®' $ûdefault² disabledserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uartœÿV È æn6®úïbaudclkapb_pclkŒ‘txrxûdefault  %&'›¥okayìbluetoothrealtek,rtl8723ds-bt ü( ( (+„€ûdefault  )*+serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uartœÿW Èæn6®ûïbaudclkapb_pclkŒ ‘txrxûdefault ,›¥okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uartœÿX Èæn6®üïbaudclkapb_pclkŒ  ‘txrxûdefault -›¥okayserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uartœÿY Èæn6®ýïbaudclkapb_pclkŒ  ‘txrxûdefault .›¥okayserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uartœÿZ Èæn6® þïbaudclkapb_pclkŒ‘txrxûdefault /›¥ disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradcœÿ^ È(5®, ïsaradcapb_pclkG; Nsaradc-apbokayZ timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timerœÿf  È® - ïpclktimervop@ffb00000rockchip,rv1126-vopœÿ°ÿ°  È;ïaclk_vopdclk_vophclk_vop®¯šÚ NaxiahbdclkG†‡ˆf0m1  disabledportÀendpoint@0œendpoint@1œiommu@ffb00f00rockchip,iommuœÿ° È; ïaclkiface®¯Ú{m1  disabledÀ0ethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20aœÿÄ@È_`ˆmacirqeth_wake_irqâ"@®~ˆˆ¿ˆ‰Tïstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_refG¾ Nstmmaceth˜©²2Â3Õ4okayè}~ˆø|}‡úð€$output15?@7ZU6a mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshcœÿÆ@ ÈL ®älmnïbiuciuciu-driveciu-sampleåð ëÂokayþnÈûdefault ABCD7Z‘ž«a mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshcœÿÇ@ ÈM ®æopqïbiuciuciu-driveciu-sampleåðúð€m1okayþn¹ÆÜE)ûdefault  FGH7ZçU a spi@ffc90000 rockchip,sfcœÿÉ@ ÈPèvÄ´ïclk_sfchclk_sfc®vêm1 disabledpinctrlrockchip,rv1126-pinctrlâ"ôgpio@ff460000rockchip,gpio-bankœÿF È"®&¡¶Àgpio@ff620000rockchip,gpio-bankœÿb È#®(¡¶À(gpio@ff630000rockchip,gpio-bankœÿc È$®)¡¶À<�gpio@ff640000rockchip,gpio-bankœÿd È%®*¡¶gpio@ff650000rockchip,gpio-bankœÿe È&® +¡¶pcfg-pull-up$ÀLpcfg-pull-down1ÀKpcfg-pull-none@ÀIpcfg-pull-none-drv-level-3@MÀNpcfg-pull-up-drv-level-2$MÀJpcfg-pull-none-drv-level-0-smt@M\ÀMclk_out_ethernetemmcemmc-rstnoutqIÀ@emmc-bus8€qJJJJJJJJÀ=emmc-clkqJÀ?emmc-cmdqJÀ>fspii2c0i2c0-xfer q M MÀi2c2i2c2-xfer qMMÀpwm2pwm2m0-pinsqIÀ!pwm11pwm11m0-pinsqIÀ$rgmiirgmiim1-miim qIIÀ7rgmiim1-rxerqIÀ8rgmiim1-bus2`q II INNNÀ9rgmiim1-mclkinoutqIÀ:sdmmc0sdmmc0-bus4@qJJJJÀCsdmmc0-clkqJÀAsdmmc0-cmdq JÀBsdmmc0-detqIÀDsdmmc1sdmmc1-bus4@q J JJJÀHsdmmc1-clkq JÀFsdmmc1-cmdq JÀGuart0uart0-xfer qLLÀ%uart0-ctsnqIÀ&uart0-rtsnqIÀ'uart1uart1m0-xfer qLLÀ uart2uart2m1-xfer qLLÀ,uart3uart3m2-xfer qLLÀ-uart4uart4m2-xfer qLLÀ.uart5uart5m0-xfer qLLÀ/etherneteth-phy-rstqKÀ;btbt-enableqIÀ)bt-wake-devqIÀ*bt-wake-hostqIÀ+pmicpmic-int-lq LÀwifiwifi-enable-hqIÀPchosenserial2:1500000n8regulator-vcc5v0-sysregulator-fixed ®vcc5v0_sys½ÑúLK@LK@Àpwrseq-sdiommc-pwrseq-simple®O ïext_clockûdefault P ƒ(ÀE #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2serial0serial1serial2serial3serial4serial5ethernet0mmc0mmc1mmc2device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosmax-speed#io-channel-cellsresetsreset-namesvref-supplyiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplyreset-active-lowreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqsd-uhs-sdr50rockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-path