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ïext_clockûdefault Nƒ&ÀC #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2serial0serial1serial2serial3serial4serial5ethernet0mmc0mmc1mmc2device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosmax-speed#io-channel-cellsresetsreset-namesvref-supplyiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplyreset-active-lowreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqsd-uhs-sdr50rockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-path