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ydisableddma-controller@ff250000arm,pl330arm,primecell?ÿ%@úbmˆ{ Bapb_pclk¨thermal-zonesreserve-thermalŸèµˆÃ@cpu-thermalŸdµˆÃ@tripscpu_alert0ÓýèßÐ:passive¨Acpu_alert1ÓpßÐ:passive¨Bcpu_critÓ_ßÐ :criticalcooling-mapsmap0êA0ïÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1êB0ïÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermalŸdµˆÃ@tripsgpu_alert0Ó8€ßÐ:passive¨Cgpu_critÓ_ßÐ :criticalcooling-mapsmap0êC ïDÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadc?ÿ( ú%{HZBtsadcapb_pclkCŸ mtsadc-apb?initdefaultsleepMEþFE(G5èHyokayLc¨@ethernet@ff290000rockchip,rk3288-gmac?ÿ)ú~macirqeth_wake_irq(G8{—fgc˜Ä]MBstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macCB mstmmaceth ydisabledusb@ff500000 generic-ehci?ÿP ú{ÂŽH“usbyokayusb@ff520000 generic-ohci?ÿR ú){ÂŽH“usb ydisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2?ÿT ú{ÃBotg³hostŽI “usb2-phy»yokayÒusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2?ÿX ú{ÁBotg³hostéû €€@@ ŽJ “usb2-phyyokayz)JÒusb@ff5c0000 generic-ehci?ÿ\ ú{Ä ydisableddma-controller@ff600000arm,pl330arm,primecell?ÿ`@úbmˆ{Á Bapb_pclk ydisabledi2c@ff650000rockchip,rk3288-i2c?ÿe ú<�Bi2c{L?defaultMKyokay×€Š2¢dpmic@1brockchip,rk808?çxin32kwifibt_32kin&0ú?defaultML@çúamy…‘M©µÂ3ÏÜMèM¨“regulatorsDCDC_REG1õvdd_arm* q°B Zq¨ regulator-state-memoDCDC_REG2õvdd_gpu* 5BÐZq¨‚regulator-state-memoDCDC_REG3 õvcc135_ddrregulator-state-memˆDCDC_REG4õvcc_18*w@Bw@¨regulator-state-memˆ w@LDO_REG1 õvcc33_io*2Z B2Z ¨3regulator-state-memˆ 2Z LDO_REG3õvdd_10*B@BB@regulator-state-memˆ B@LDO_REG7õvdd10_lcd_pwren_h*&% B&% regulator-state-memoSWITCH_REG1 õvcc33_lcd¨cregulator-state-memoLDO_REG6 õvcc18_codec*w@Bw@¨dregulator-state-memoLDO_REG4 õvccio_sd*w@B2Z ¨regulator-state-memoLDO_REG5 õvcc33_sd*2Z B2Z ¨regulator-state-memoLDO_REG8 õvcc33_ccd*2Z B2Z regulator-state-memoi2c@ff660000rockchip,rk3288-i2c?ÿf ú=Bi2c{N?defaultMNyokay׆ Š2¢ max98090@10maxim,max98090?&OúBmclk{q?defaultMP¨pwm@ff680000rockchip,rk3288-pwm?ÿh¼?defaultMQ{_yokay¨¤pwm@ff680010rockchip,rk3288-pwm?ÿh¼?defaultMR{_yokay¨™pwm@ff680020rockchip,rk3288-pwm?ÿh ¼?defaultMS{_ ydisabledpwm@ff680030rockchip,rk3288-pwm?ÿh0¼?defaultMT{_ ydisabledsram@ff700000 mmio-sram?ÿp€Ðÿp€smp-sram@0rockchip,rk3066-smp-sram?sram@ff720000#rockchip,rk3288-pmu-srammmio-sram?ÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd?ÿs¨power-controller!rockchip,rk3288-power-controllerÇh) ¨hpower-domain@9? È{ÊÍÈÌÅƾ¿ÔÕÖÙÑÒchgfdehilkj$ÛUVWXYZ[\]Çpower-domain@11? {ÏopÛ^_Çpower-domain@12? {ÐÜÛ`Çpower-domain@13? {ÀÛabÇreboot-modesyscon-reboot-modeâ”éRBÃõRBà RBà  RBÃsyscon@ff740000rockchip,rk3288-sgrfsyscon?ÿtclock-controller@ff760000rockchip,rk3288-cru?ÿv{ Bxin24m(Gú HÑÝjÒÞk$ ,#g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀ¨syscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd?ÿw¨Gedp-phyrockchip,rk3288-dp-phy{hB24m Ayokay¨xio-domains"rockchip,rk3288-io-voltage-domainyokay L3 V a o3 3 c ™ ¥d ²usbphyrockchip,rk3288-usb-phyyokayusb-phy@320 A? {]BphyclkúC… mphy-reset¨Jusb-phy@334 A?4{^BphyclkúCˆ mphy-reset¨Husb-phy@348 A?H{_BphyclkúC‹ mphy-reset¨Iwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt?ÿ€{p úOyokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif?ÿ‹ À{TÐ Bmclkhclk´e¹tx ú6?defaultMf(G ydisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s?ÿ‰ À ú5{RÎBi2s_clki2s_hclk´ee¹txrx?defaultMg Ñ ìyokay¨œcrypto@ff8a0000rockchip,rk3288-crypto?ÿŠ@ ú0 {ÇÍ}ÁBaclkhclksclkapb_pclkC® mcrypto-rstiommu@ff900800rockchip,iommu?ÿ@ ú{ÊÔ Baclkiface  ydisablediommu@ff914000rockchip,iommu ?ÿ‘@ÿ‘P ú{ÍÕ Baclkiface   ydisabledrga@ff920000rockchip,rk3288-rga?ÿ’€ ú{ÈÖjBaclkhclksclk .h Cilm mcoreaxiahbvop@ff930000rockchip,rk3288-vop ?ÿ“œÿ“ ú{žÑBaclk_vopdclk_vophclk_vop .h Cdef maxiahbdclk <�iyokayport¨ endpoint@0? Cj¨~endpoint@1? Ck¨yendpoint@2? Cl¨sendpoint@3? Cm¨viommu@ff930300rockchip,iommu?ÿ“ ú{ÅÑ Baclkiface .h  yokay¨ivop@ff940000rockchip,rk3288-vop ?ÿ”œÿ” ú{Æ¿ÒBaclk_vopdclk_vophclk_vop .h C°±² maxiahbdclk <�nyokayport¨ endpoint@0? Co¨endpoint@1? Cp¨zendpoint@2? Cq¨tendpoint@3? Cr¨wiommu@ff940300rockchip,iommu?ÿ” ú{ÆÒ Baclkiface .h  yokay¨ndsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi?ÿ–@ ú{~d Brefpclk .h (G ydisabledportsport@0?endpoint@0? Cs¨lendpoint@1? Ct¨qport@1?lvds@ff96c000rockchip,rk3288-lvds?ÿ–À@{g Bpclk_lvds?lcdcMu .h (G ydisabledportsport@0?endpoint@0? Cv¨mendpoint@1? Cw¨rport@1?dp@ff970000rockchip,rk3288-dp?ÿ—@ úb{icBdppclkŽx“dp .h Comdp(Gyokay Sportsport@0?endpoint@0? Cy¨kendpoint@1? Cz¨pport@1?endpoint@0? C{¨¨hdmi@ff980000rockchip,rk3288-dw-hdmi?ÿ˜ÿ úg{hmnBiahbisfrcec .h (G Àyokay?defaultunwedgeM|þ}¨Ÿportsport@0?endpoint@0? C~¨jendpoint@1? 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¨^qos@ffaf0080rockchip,rk3288-qossyscon?ÿ¯€ ¨_dma-controller@ffb20000arm,pl330arm,primecell?ÿ²@úbmˆ{Á Bapb_pclk¨eefuse@ffb40000rockchip,rk3288-efuse?ÿ´ {q Bpclk_efusecpu-id@7?cpu_leakage@17?interrupt-controller@ffc01000 arm,gic-400 i ~@?ÿÀÿÀ ÿÀ@ ÿÀ`  ú ¨pinctrlrockchip,rk3288-pinctrl(G&Ð?defaultsleepMƒ„…†þƒ„…‡gpio@ff750000rockchip,gpio-bank?ÿu úQ{@  Ÿ i ~ç «PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INT¨0gpio@ff780000rockchip,gpio-bank?ÿx úR{A  Ÿ i ~gpio@ff790000rockchip,gpio-bank?ÿy úS{B  Ÿ i ~Z «CONFIG0CONFIG1CONFIG2CONFIG3PWRLIMIT#_CPUEMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_EN¨’gpio@ff7a0000rockchip,gpio-bank?ÿz úT{C  Ÿ i ~‚ «FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank?ÿ{ úU{D  Ÿ i ~³ «UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKE¨;gpio@ff7c0000rockchip,gpio-bank?ÿ| úV{E  Ÿ i ~A «SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_EN¨—gpio@ff7d0000rockchip,gpio-bank?ÿ} úW{F  Ÿ i ~° «I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMD¨Ogpio@ff7e0000rockchip,gpio-bank?ÿ~ úX{G  Ÿ i ~ß «LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVS_OKEDP_HOTPLUGDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXD¨ gpio@ff7f0000rockchip,gpio-bank?ÿ úY{H  Ÿ i ~^ «RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 »ˆhdmi-cec-c7 »ˆhdmi-ddc »ˆˆ¨|hdmi-ddc-unwedge »‰ˆ¨}vcc50-hdmi-en »ˆ¨˜pcfg-output-low ɨ‰pcfg-pull-up Ô¨Špcfg-pull-down ᨌpcfg-pull-none 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-params#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type