Ð þ힆8•„( •L7radxa,rockpi-n8vamrs,rk3288-vmarc-somrockchip,rk3288&7Radxa ROCK Pi N8aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000‚/i2c@ff140000‡/i2c@ff660000Œ/i2c@ff150000‘/i2c@ff160000–/i2c@ff170000›/mmc@ff0f0000¡/mmc@ff0c0000§/mmc@ff0d0000­/mmc@ff0e0000³/serial@ff180000»/serial@ff190000Ã/serial@ff690000Ë/serial@ff1b0000Ó/serial@ff1c0000Û/spi@ff110000à/spi@ff120000å/spi@ff130000arm-pmuarm,cortex-a12-pmu0ê—˜™šõcpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]œ@krrŒcpu@501#cpuarm,cortex-a12/3:N]œ@krrŒcpu@502#cpuarm,cortex-a12/3:N]œ@krrŒcpu@503#cpuarm,cortex-a12/3:N]œ@krrŒopp-table-0operating-points-v2”Œopp-126000000Ÿ‚›€¦ » opp-216000000Ÿ ßæ¦ » opp-312000000Ÿ˜¾¦ » opp-408000000ŸQ–¦ » opp-600000000Ÿ#ÃF¦ » opp-696000000Ÿ)|¦~ðopp-816000000Ÿ0£,¦B@opp-1008000000Ÿ<ܦopp-1200000000ŸG†Œ¦Èàopp-1416000000ŸTfr¦O€opp-1512000000ŸZJ¦Ö opp-1608000000Ÿ_Ø"¦™preserved-memory´dma-unusable@fe000000/þoscillator fixed-clock»n6Ëxin24mÞŒ timerarm,armv7-timerë0ê   »n6timer@ff810000rockchip,rk3288-timer/ÿ  êH ka  &pclktimerdisplay-subsystemrockchip,display-subsystem2 mmc@ff0c0000rockchip,rk3288-dw-mshc8ðÑ€ kÈDrv&biuciuciu-driveciu-sampleF ê /ÿ @3€Qreset]okaydn€‘œ ©default· mmc@ff0d0000rockchip,rk3288-dw-mshc8ðÑ€ kÉEsw&biuciuciu-driveciu-sampleF ê!/ÿ @3Qreset]okayd€ÁÎäï©default ·ýmmc@ff0e0000rockchip,rk3288-dw-mshc8ðÑ€ kÊFtx&biuciuciu-driveciu-sampleF ê"/ÿ@3‚Qreset ]disabledmmc@ff0f0000rockchip,rk3288-dw-mshc8ðÑ€ kËGuy&biuciuciu-driveciu-sampleF ê#/ÿ@3ƒQreset]okaydn‘ï©default· œsaradc@ff100000rockchip,saradc/ÿ ê$kI[&saradcapb_pclk3W Qsaradc-apb ]disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR&spiclkapb_pclk)  .txrx ê,©default·/ÿ ]disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS&spiclkapb_pclk) .txrx ê-©default· !"#/ÿ ]disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT&spiclkapb_pclk).txrx ê.©default·$%&'/ÿ ]disabledi2c@ff140000rockchip,rk3288-i2c/ÿ ê>&i2ckM©default·(]okay»€rtc@51haoyu,hym8563/Q&)êÞËhym8563©default·*Œi2c@ff150000rockchip,rk3288-i2c/ÿ ê?&i2ckO©default·+ ]disabledi2c@ff160000rockchip,rk3288-i2c/ÿ ê@&i2ckP©default·, ]disabledi2c@ff170000rockchip,rk3288-i2c/ÿ êA&i2ckQ©default·-]okayŒrserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê78BkMU&baudclkapb_pclk).txrx©default·./]okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê88BkNV&baudclkapb_pclk).txrx©default·0 ]disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿi ê98BkOW&baudclkapb_pclk©default·1]okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê:8BkPX&baudclkapb_pclk).txrx©default·2 ]disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê;8BkQY&baudclkapb_pclk)  .txrx©default·3 ]disableddma-controller@ff250000arm,pl330arm,primecell/ÿ%@êOZuk &apb_pclkŒthermal-zonesreserve-thermalŒè¢ˆ°4cpu-thermalŒd¢ˆ°4tripscpu_alert0ÀpÌÐ*passiveŒ5cpu_alert1À$øÌÐ*passiveŒ6cpu_critÀ_ÌÐ *criticalcooling-mapsmap0×50Üÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1×60Üÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermalŒd¢ˆ°4tripsgpu_alert0ÀpÌÐ*passiveŒ7gpu_critÀ_ÌÐ *criticalcooling-mapsmap0×7 Ü8ÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadc/ÿ( ê%kHZ&tsadcapb_pclk3Ÿ Qtsadc-apb©initdefaultsleep·9ë:õ9ÿ;"s ]disabledŒ4ethernet@ff290000rockchip,rk3288-gmac/ÿ)ê9macirqeth_wake_irq;8k—fgc˜Ä]M&stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B Qstmmaceth]okayI<�`inputmrgmii©default·=v Œ'ÃP¡(ª³—à Î>usb@ff500000 generic-ehci/ÿP êkÂÞ?ãusb]okayusb@ff520000 generic-ohci/ÿR ê)kÂÞ?ãusb]okayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿT êkÃ&otgíhostÞ@ ãusb2-phyõ]okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿX êkÁ&otgíotg -€€@@ ÞA ãusb2-phy]okayusb@ff5c0000 generic-ehci/ÿ\ êkÄ ]disableddma-controller@ff600000arm,pl330arm,primecell/ÿ`@êOZukÁ &apb_pclk ]disabledi2c@ff650000rockchip,rk3288-i2c/ÿe ê<�&i2ckL©default·B]okay»€pmic@1brockchip,rk808/&Cê©default·DE<�]ÞËrk808-clkout1rk808-clkout2kFwFƒFF›F§F³¿ËFØFåòregulatorsDCDC_REG1ÿvdd_arm"4 q°L\Àregulator-state-memdDCDC_REG2ÿvdd_gpu"4 øPLÐ}pregulator-state-memdDCDC_REG3ÿvcc_ddr"regulator-state-mem’DCDC_REG4ÿvcc_io"42Z L2Z Œregulator-state-mem’ª2Z LDO_REG1ÿvcc_tp"42Z L2Z regulator-state-memdLDO_REG2 ÿvcca_codec"42Z L2Z regulator-state-mem’ª2Z LDO_REG3ÿvdd_10"4B@LB@regulator-state-mem’ªB@LDO_REG4ÿvcc_wl"4w@Lw@Œ[regulator-state-mem’LDO_REG5 ÿvccio_sd"4w@L2Z Œ regulator-state-mem’ª2Z LDO_REG6 ÿvdd10_lcd"4B@LB@regulator-state-memdLDO_REG7ÿvcc_18"4w@Lw@ŒZregulator-state-mem’ªw@LDO_REG8 ÿvcc18_lcd"4w@Lw@regulator-state-memdSWITCH_REG1ÿvcc_sd"regulator-state-memdSWITCH_REG2ÿvcc_lcd"regulator-state-memdi2c@ff660000rockchip,rk3288-i2c/ÿf ê=&i2ckN©default·G ]disabledpwm@ff680000rockchip,rk3288-pwm/ÿhÆ©default·Hk_]okaypwm@ff680010rockchip,rk3288-pwm/ÿhÆ©default·Ik_ ]disabledpwm@ff680020rockchip,rk3288-pwm/ÿh Æ©default·Jk_]okaypwm@ff680030rockchip,rk3288-pwm/ÿh0Æ©default·Kk_ ]disabledsram@ff700000 mmio-sram/ÿp€´ÿp€smp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/ÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/ÿsŒpower-controller!rockchip,rk3288-power-controllerѳhI Œ_power-domain@9/ ÈkÊÍÈÌÅƾ¿ÔÕÖÙÑÒchgfdehilkj$åLMNOPQRSTÑpower-domain@11/ kÏopåUVÑpower-domain@12/ kÐÜåWÑpower-domain@13/ kÀåXYÑreboot-modesyscon-reboot-modeì”óRBÃÿRBà RBà RBÃsyscon@ff740000rockchip,rk3288-sgrfsyscon/ÿtclock-controller@ff760000rockchip,rk3288-cru/ÿvk &xin24m;Þ)H³ÑÝjÒÞk$6#g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀŒsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/ÿwŒ;edp-phyrockchip,rk3288-dp-phykh&24mK ]disabledŒoio-domains"rockchip,rk3288-io-voltage-domain]okayV`nZ~Œ š[usbphyrockchip,rk3288-usb-phy]okayusb-phy@320K/ k]&phyclkÞ3… Qphy-resetŒAusb-phy@334K/4k^&phyclkÞ3ˆ Qphy-resetŒ?usb-phy@348K/Hk_&phyclkÞ3‹ Qphy-resetŒ@watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/ÿ€kp êO ]disabledsound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/ÿ‹¦kTÐ &mclkhclk)\.tx ê6©default·]; ]disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ÿ‰¦ ê5kRÎ&i2s_clki2s_hclk)\\.txrx©default·^·Ò ]disabledcrypto@ff8a0000rockchip,rk3288-crypto/ÿŠ@ ê0 kÇÍ}Á&aclkhclksclkapb_pclk3® Qcrypto-rstiommu@ff900800rockchip,iommu/ÿ@ êkÊÔ &aclkifaceì ]disablediommu@ff914000rockchip,iommu /ÿ‘@ÿ‘P êkÍÕ &aclkifaceìù ]disabledrga@ff920000rockchip,rk3288-rga/ÿ’€ êkÈÖj&aclkhclksclk_ 3ilm Qcoreaxiahbvop@ff930000rockchip,rk3288-vop /ÿ“œÿ“ êkžÑ&aclk_vopdclk_vophclk_vop_ 3def Qaxiahbdclk"`]okayportŒ endpoint@0/)aŒtendpoint@1/)bŒpendpoint@2/)cŒjendpoint@3/)dŒmiommu@ff930300rockchip,iommu/ÿ“ êkÅÑ &aclkiface_ ì]okayŒ`vop@ff940000rockchip,rk3288-vop /ÿ”œÿ” êkÆ¿Ò&aclk_vopdclk_vophclk_vop_ 3°±² Qaxiahbdclk"e]okayportŒ endpoint@0/)fŒuendpoint@1/)gŒqendpoint@2/)hŒkendpoint@3/)iŒniommu@ff940300rockchip,iommu/ÿ” êkÆÒ &aclkiface_ ì]okayŒedsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/ÿ–@ êk~d &refpclk_ ; ]disabledportsport@0/endpoint@0/)jŒcendpoint@1/)kŒhport@1/lvds@ff96c000rockchip,rk3288-lvds/ÿ–À@kg &pclk_lvds©lcdc·l_ ; ]disabledportsport@0/endpoint@0/)mŒdendpoint@1/)nŒiport@1/dp@ff970000rockchip,rk3288-dp/ÿ—@ êbkic&dppclkÞoãdp_ 3oQdp; ]disabledportsport@0/endpoint@0/)pŒbendpoint@1/)qŒgport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/ÿ˜B êgkhmn&iahbisfrcec_ ;¦]okay9r©default·sportsport@0/endpoint@0/)tŒaendpoint@1/)uŒfport@1/video-codec@ff9a0000rockchip,rk3288-vpu/ÿšê   9vepuvdpukÐÜ &aclkhclk"v_ iommu@ff9a0800rockchip,iommu/ÿš ê kÐÜ &aclkifaceì_ Œviommu@ff9c0440rockchip,iommu /ÿœ@@ÿœ€@ êokÏÛ &aclkifaceì ]disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/ÿ£$ê 9jobmmugpukÀ:wN_  ]disabledŒ8opp-table-1operating-points-v2Œwopp-100000000Ÿõá¦~ðopp-200000000Ÿ ë¦~ðopp-300000000Ÿá£¦B@opp-400000000Ÿׄ¦Èàopp-600000000Ÿ#ÃF¦Ðqos@ffaa0000rockchip,rk3288-qossyscon/ÿª ŒXqos@ffaa0080rockchip,rk3288-qossyscon/ÿª€ ŒYqos@ffad0000rockchip,rk3288-qossyscon/ÿ­ ŒMqos@ffad0100rockchip,rk3288-qossyscon/ÿ­ ŒNqos@ffad0180rockchip,rk3288-qossyscon/ÿ­€ ŒOqos@ffad0400rockchip,rk3288-qossyscon/ÿ­ ŒPqos@ffad0480rockchip,rk3288-qossyscon/ÿ­€ ŒQqos@ffad0500rockchip,rk3288-qossyscon/ÿ­ ŒLqos@ffad0800rockchip,rk3288-qossyscon/ÿ­ ŒRqos@ffad0880rockchip,rk3288-qossyscon/ÿ­€ ŒSqos@ffad0900rockchip,rk3288-qossyscon/ÿ­ ŒTqos@ffae0000rockchip,rk3288-qossyscon/ÿ® ŒWqos@ffaf0000rockchip,rk3288-qossyscon/ÿ¯ ŒUqos@ffaf0080rockchip,rk3288-qossyscon/ÿ¯€ ŒVdma-controller@ffb20000arm,pl330arm,primecell/ÿ²@êOZukÁ &apb_pclkŒ\efuse@ffb40000rockchip,rk3288-efuse/ÿ´ kq &pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400EZ@/ÿÀÿÀ ÿÀ@ ÿÀ`  ê Œpinctrlrockchip,rk3288-pinctrl;´gpio@ff750000rockchip,gpio-bank/ÿu êQk@k{EZŒCgpio@ff780000rockchip,gpio-bank/ÿx êRkAk{EZgpio@ff790000rockchip,gpio-bank/ÿy êSkBk{EZgpio@ff7a0000rockchip,gpio-bank/ÿz êTkCk{EZgpio@ff7b0000rockchip,gpio-bank/ÿ{ êUkDk{EZŒ>gpio@ff7c0000rockchip,gpio-bank/ÿ| êVkEk{EZŒ)gpio@ff7d0000rockchip,gpio-bank/ÿ} êWkFk{EZgpio@ff7e0000rockchip,gpio-bank/ÿ~ êXkGk{EZgpio@ff7f0000rockchip,gpio-bank/ÿ êYkHk{EZhdmihdmi-cec-c0‡xŒshdmi-cec-c7‡xhdmi-ddc ‡xxhdmi-ddc-unwedge ‡yxpcfg-output-low•Œypcfg-pull-up Œzpcfg-pull-down­Œ{pcfg-pull-none¼Œxpcfg-pull-none-12ma¼É Œ~suspendglobal-pwroff‡xŒEddrio-pwroff‡xddr0-retention‡zddr1-retention‡zedpedp-hpd‡ {i2c0i2c0-xfer ‡xxŒBi2c1i2c1-xfer ‡xxŒ(i2c2i2c2-xfer ‡ x xŒGi2c3i2c3-xfer ‡xxŒ+i2c4i2c4-xfer ‡xxŒ,i2c5i2c5-xfer ‡xxŒ-i2s0i2s0-bus`‡xxxxxxŒ^lcdclcdc-ctl@‡xxxxŒlsdmmcsdmmc-clk‡|Œ sdmmc-cmd‡}Œsdmmc-cd‡zŒsdmmc-bus1‡zsdmmc-bus4@‡}}}}Œsdio0sdio0-bus1‡zsdio0-bus4@‡zzzzŒsdio0-cmd‡zŒsdio0-clk‡xŒsdio0-cd‡zsdio0-wp‡zsdio0-pwr‡zsdio0-bkpwr‡zsdio0-int‡zsdio1sdio1-bus1‡zsdio1-bus4@‡zzzzsdio1-cd‡zsdio1-wp‡zsdio1-bkpwr‡zsdio1-int‡zsdio1-cmd‡zsdio1-clk‡xsdio1-pwr‡ zemmcemmc-clk‡xŒemmc-cmd‡zŒemmc-pwr‡ zŒemmc-bus1‡zemmc-bus4@‡zzzzemmc-bus8€‡zzzzzzzzŒspi0spi0-clk‡ zŒspi0-cs0‡ zŒspi0-tx‡zŒspi0-rx‡zŒspi0-cs1‡zspi1spi1-clk‡ zŒ spi1-cs0‡ zŒ#spi1-rx‡zŒ"spi1-tx‡zŒ!spi2spi2-cs1‡zspi2-clk‡zŒ$spi2-cs0‡zŒ'spi2-rx‡zŒ&spi2-tx‡ zŒ%uart0uart0-xfer ‡zxŒ.uart0-cts‡zŒ/uart0-rts‡xuart1uart1-xfer ‡z xŒ0uart1-cts‡ zuart1-rts‡ xuart2uart2-xfer ‡zxŒ1uart3uart3-xfer ‡zxŒ2uart3-cts‡ zuart3-rts‡ xuart4uart4-xfer ‡zxŒ3uart4-cts‡ zuart4-rts‡ xtsadcotp-pin‡ xŒ9otp-out‡ xŒ:pwm0pwm0-pin‡xŒHpwm1pwm1-pin‡xŒIpwm2pwm2-pin‡xŒJpwm3pwm3-pin‡xŒKgmacrgmii-pinsð‡xxxx~~~~xxx ~~xxŒ=rmii-pins ‡xxxxxxxxxxspdifspdif-tx‡ xŒ]hym8563hym8563-int‡zŒ*pcfg-pull-none-drv-8maÉŒ|pcfg-pull-up-drv-8ma ÉŒ}pmicpmic-int‡zŒDsdio-pwrseqwifi-enable-h‡xŒ€vbus_hostusb1-en-oc‡zŒ‚vbus_typecusb0-en-oc‡ zŒƒexternal-gmac-clock fixed-clock»sY@ Ëclkin_gmacÞŒ<�sdio-pwrseqmmc-pwrseq-simplek &ext_clock©default·€ Ø>Œvcc12v-dcin-regulatorregulator-fixed ÿvcc12v_dcin"4·L·Œvcc5v0-sys-regulatorregulator-fixed ÿvcc5v0_sys"4LK@LLK@䁌Fvbus-hostregulator-fixed©default·‚ ÿvbus_hostäFï ÙCvbus-typecregulator-fixed©default·ƒ ÿvbus_typecäFï ÙC vccio-flash-regulatorregulator-fixed ÿvccio_flash4w@Lw@äŒ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvqmmc-supplypinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104vmmc-supply#io-channel-cellsdmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-tempinterrupt-namesassigned-clock-parentsclock_in_outphy-modesnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayassigned-clocksphy-supplysnps,reset-gpiophysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-off-in-suspendregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplyflash0-supplygpio1830-supplygpio30-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthreset-gpiosvin-supplyenable-active-high