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þí^Ì8Z@(ŒZ$rockchip,rk3128-evbrockchip,rk3128+!7Rockchip RK3128 Evaluation boardaliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000/mmc@1021c000arm-pmuarm,cortex-a7-pmu0†LMNO‘cpus+¤rockchip,rk3036-smpcpu@f00²cpuarm,cortex-a7¾Âœ@Ð×Þòcpu@f01²cpuarm,cortex-a7¾×Þcpu@f02²cpuarm,cortex-a7¾×Þcpu@f03²cpuarm,cortex-a7¾×Þopp-table-0operating-points-v2 opp-216000000ßæ~ð~ð7Èopp-408000000Q–~ð~ð7Èopp-600000000#ÃF~ð~ð7Èopp-696000000)|à˜à˜7Èopp-8160000000£,g8g87È)opp-1008000000<ÜO€O€7Èopp-1200000000G†Œ7È7È7Èdisplay-subsystemrockchip,display-subsystem5 ;disabledopp-table-1operating-points-v2 opp-200000000ëÂà˜à˜Ðopp-300000000á£Ðopp-400000000ׄŒ0Œ0Ðopp-480000000œ8ÐÐÐtimerarm,armv7-timer0†
Bfn6oscillatorfixed-clockfn6vxin24m‰(sram@10080000
mmio-sram¾ +– smp-sram@0rockchip,rk3066-smp-sram¾gpu@10090000"rockchip,rk3128-maliarm,mali-400¾ H†gpgpmmupp0ppmmu0pp1ppmmu1ÐÕÕ buscoreÞ ×x¹
;disabledsyscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd¾
power-controller!rockchip,rk3128-power-controllerÇ+
power-domain@1¾˜ÐÆÖ¿ÑÇÔÌÏEr”ÍÓÀÁÒÕ¾zÛ
Çpower-domain@2¾(ÐÅÎÄ͆ÛÇpower-domain@3¾ÐÕÛÇvop@1010e000rockchip,rk3126-vop¾à† Ð̾Ïaclk_vopdclk_vophclk_vop×def
âaxiahbdclk¹
;disabledport+endpoint@0¾î-endpoint@1¾îdsi@10110000*rockchip,rk3128-mipi-dsisnps,dw-mipi-dsi¾@†!ÐEpclkþdphy¹
׉âapb
;disabledports+port@0¾endpointîport@1¾qos@1012d000rockchip,rk3128-qossyscon¾Ð qos@1012e000rockchip,rk3128-qossyscon¾à qos@1012f000rockchip,rk3128-qossyscon¾ð qos@1012f080rockchip,rk3128-qossyscon¾ð€ qos@1012f100rockchip,rk3128-qossyscon¾ñ qos@1012f180rockchip,rk3128-qossyscon¾ñ€
qos@1012f200rockchip,rk3128-qossyscon¾ò interrupt-controller@10139000arm,cortex-a7-gic ¾ À à † /usb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2¾†
ÐÚotg@otgHZi€€@ þ usb2-phy;okayxusb@101c0000
generic-ehci¾†ÐÙþusb;okayusb@101e0000
generic-ohci¾† ÐÙþusb;okayi2s@10200000(rockchip,rk3128-i2srockchip,rk3066-i2s¾ †DÐP»i2s_clki2s_hclk„‰txrx“ ;disabledspdif@10204000,rockchip,rk3128-spdifrockchip,rk3066-spdif¾ @†7ÐS¸
mclkhclk„
‰tx¤default²“ ;disabledspi@1020c000
rockchip,sfc¾ À€†2Йßclk_sfchclk_sfc ;disabledmmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!@@† ÐÈDrvbiuciuciu-driveciu-sample„
‰rx-tx¼ÇðÑ€×Qâreset ;disabledmmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!€@† ÐÉEswbiuciuciu-driveciu-sample„‰rx-tx¼ÇðÑ€×Râreset ;disabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!À@† ÐËGuybiuciuciu-driveciu-sample„‰rx-tx¼ÇðÑ€×Sâreset;okayÕ¤default²i2s@10220000(rockchip,rk3128-i2srockchip,rk3066-i2s¾"†ÐQ¼i2s_clki2s_hclk„‰txrxߤdefault²“ ;disablednand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfc¾P@†ÐÅCahbnfc¤default ² !"#$%&' ;disabledclock-controller@20000000rockchip,rk3128-cru¾ Ð(xin24m
‰ú#g¸€syscon@20008000&rockchip,rk3128-grfsysconsimple-mfd¾ €+usb2phy@17crockchip,rk3128-usb2phy¾|ÐŽphyclkvusb480m_phyš,)‰;okay)host-port†5
linestateC;okayotg-port$†#34otg-bvalidotg-idlinestateC;okayhdmi@20034000rockchip,rk3128-inno-hdmi¾ @@†-ÐG¾ pclkref¤default²*+,¹
“ ;disabledports+port@0¾endpointî-port@1¾phy@20038000rockchip,rk3128-dsi-dphy¾ €@Дr refpclkC¹
×$âapb ;disabledtimer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer¾ @ †ÐaUpclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer¾ @ †ÐaVpclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer¾ @@ †;ÐaWpclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer¾ @` †<�ÐaXpclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer¾ @€ †=ÐaYpclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer¾ @ †>ÐaZpclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt¾ À†"Ð? ;disabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Ð^¤default².N ;disabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Ð^¤default²/N ;disabledpwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Ð^¤default²0N ;disabledpwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ 0Ð^¤default²1N ;disabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ `†i2cÐM¤default²2+;okayrtc@51haoyu,hym8563¾Q‰vxin32ki2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ †i2cÐN¤default²3+ ;disabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ à†i2cÐO¤default²4+ ;disabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart¾ †fn6ÐMUbaudclkapb_pclk„‰txrx¤default²567Yf ;disabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart¾ @†fn6ÐNVbaudclkapb_pclk„‰txrx¤default²8Yf ;disabledserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart¾ €†fn6ÐOWbaudclkapb_pclk„‰txrx¤default²9Yf ;disabledsaradc@2006c000rockchip,saradc¾ À†Ð[>saradcapb_pclk×Wâsaradc-apbp ;disabledi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ †i2cÐL¤default²:+ ;disabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi¾ @†ÐARspiclkapb_pclk„ ‰txrx¤default²;<�=>?+ ;disableddma-controller@20078000arm,pl330arm,primecell¾ €@†‚Рapb_pclk´ethernet@2008c000rockchip,rk3128-gmac¾ À@†89macirqeth_wake_irq8Ð~‚€ÔoMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac×8
âstmmaceth
¿Í ;disabledmdiosnps,dwmac-mdio+pinctrlrockchip,rk3128-pinctrl
+–gpio@2007c000rockchip,gpio-bank¾ À†$Ð@Ûë/Bgpio@20080000rockchip,gpio-bank¾ †%ÐAÛë/gpio@20084000rockchip,gpio-bank¾ @†&ÐBÛë/Dgpio@20088000rockchip,gpio-bank¾ €†'ÐCÛë/pcfg-pull-default÷Apcfg-pull-none
@emmcemmc-clk@emmc-cmdAemmc-cmd1Aemmc-pwrAemmc-bus1Aemmc-bus4@AAAAemmc-bus8€AAAAAAAAgmacrgmii-pinsðA AAA
AAAAAAAAAAArmii-pins AA
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@@i2s1-bus`@@@@@@lcdclcdc-dclk@lcdc-den@lcdc-hsync @lcdc-vsync
@lcdc-rgb24à@
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A<�spi0-cs1A?spi1-clkAspi1-cs0Aspi1-txAspi1-rxAspi1-cs1Aspi2-clk Aspi2-cs0Aspi2-txAspi2-rx
Auart0uart0-xfer A@5uart0-cts@6uart0-rts@7uart1uart1-xfer A
A8uart1-cts@uart1-rts@uart2uart2-xfer A@9uart2-cts@uart2-rts@usb-hosthost-vbus-drv@Eusb-otgotg-vbus-drv@Cchosen(/serial@20068000memory@60000000²memory¾`@vcc5v0-otg-regulatorregulator-fixed4B¤default²C9vcc5v0_otgHLK@`LK@vcc5v0-host-regulatorregulator-fixed4D¤default²E9vcc5v0_hostxHLK@`LK@ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2mmc0interruptsinterrupt-affinityenable-methoddevice_typeregclock-latencyclocksresetsoperating-points-v2#cooling-cellsphandleopp-sharedopp-hzopp-microvoltopp-suspendportsstatusarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domains#power-domain-cellspm_qosreset-namesremote-endpointphysphy-namesrockchip,grfinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizevbus-supplydmasdma-names#sound-dai-cellspinctrl-namespinctrl-0fifo-depthmax-frequencybus-widthrockchip,playback-channels#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathgpioregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on