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Š/ocp/dsp‘/ocp/ipu@55020000cpus+cpu@0arm,cortex-a9˜cpu¤µ¹ÀcpuÌ“à Ú“à£è 'ÀO€ 5èa€ûëú•cpu@1arm,cortex-a9˜cpu¤µsram@40304000 mmio-sramµ@0@ ú~interrupt-controller@48241000arm,cortex-a9-gicµH$H$ úcache-controller@48242000arm,pl310-cacheµH$ (6úlocal-timer@48240600arm,cortex-a9-twd-timer¹µH$  B  interrupt-controller@48281000ti,omap4-wugen-mpuµH( úocpsimple-pm-busM$¹ +[l3-noc@44000000ti,omap4-l3-nocµDD€ EB  interconnect@4a300000ti,omap4-l4-wkupsimple-pm-busM  ¹ ÀfckµJ0J0J0 baplaia0+$[J0J1J2segment@0simple-pm-bus+„[`` €€  °°@@PPÀÀÐÐtarget-module@4000ti,sysc-omap2ti,syscµ@@ brevsyscl ¹ 0Àfck+ [@counter@0ti,omap-counter32kµ target-module@6000ti,sysc-omap4ti,syscµ`brev+ [` prm@0ti,omap4-prmsimple-busµ  B + [ clocks+sys_clkin_ck@110z ti,mux-clock ‡sys_clkin_ck¹ µšúabe_dpll_bypass_clk_mux_ck@108z ti,mux-clock‡abe_dpll_bypass_clk_mux_ck¹±µú9abe_dpll_refclk_mux_ck@10cz ti,mux-clock‡abe_dpll_refclk_mux_ck¹µ ú8dbgclk_mux_ckzfixed-factor-clock‡dbgclk_mux_ck¹¾Él4_wkup_clk_mux_ck@108z ti,mux-clock‡l4_wkup_clk_mux_ck¹µsyc_clk_div_ck@100zti,divider-clock‡syc_clk_div_ck¹µÓú€usim_ck@1858zti,divider-clock‡usim_ck¹±µXÞúusim_fclk@1858zti,gate-clock ‡usim_fclk¹±µXtrace_clk_div_ckzti,clkdm-gate-clock‡trace_clk_div_ck ¹úbandgap_fclk@1888zti,gate-clock ‡bandgap_fclk¹±µˆclockdomainsemu_sys_clkdmti,clockdomain‡emu_sys_clkdm¹l4_wkup_cm@1800 ti,omap4-cm ‡l4_wkup_cmµ+ [clk@20 ti,clkctrl‡l4_wkup_clkctrlµ \zú emu_sys_cm@1a00 ti,omap4-cm ‡emu_sys_cmµ+ [clk@20 ti,clkctrl‡emu_sys_clkctrlµ zúprm@300#ti,omap4-prm-instti,omap-prm-instµêú|prm@400#ti,omap4-prm-instti,omap-prm-instµþêúcprm@500#ti,omap4-prm-instti,omap-prm-instµêúprm@600#ti,omap4-prm-instti,omap-prm-instµêprm@700#ti,omap4-prm-instti,omap-prm-instµþêú4prm@f00#ti,omap4-prm-instti,omap-prm-instµþêúprm@1000#ti,omap4-prm-instti,omap-prm-instµêúprm@1100#ti,omap4-prm-instti,omap-prm-instµ@êúŽprm@1200#ti,omap4-prm-instti,omap-prm-instµêú‹prm@1300#ti,omap4-prm-instti,omap-prm-instµêprm@1400#ti,omap4-prm-instti,omap-prm-instµêúprm@1600#ti,omap4-prm-instti,omap-prm-instµêprm@1700#ti,omap4-prm-instti,omap-prm-instµêú prm@1900#ti,omap4-prm-instti,omap-prm-instµêú‚prm@1b00#ti,omap4-prm-instti,omap-prm-instµ@þtarget-module@a000ti,sysc-omap4ti,syscµ brev+ [ scrm@0ti,omap4-scrmµ clocks+auxclk0_src_gate_ck@310z ti,composite-no-wait-gate-clock‡auxclk0_src_gate_ck¹±µúauxclk0_src_mux_ck@310zti,composite-mux-clock‡auxclk0_src_mux_ck ¹±µúauxclk0_src_ckzti,composite-clock‡auxclk0_src_ck¹úauxclk0_ck@310zti,divider-clock ‡auxclk0_ck¹±Óµú.auxclk1_src_gate_ck@314z ti,composite-no-wait-gate-clock‡auxclk1_src_gate_ck¹±µúauxclk1_src_mux_ck@314zti,composite-mux-clock‡auxclk1_src_mux_ck ¹±µú auxclk1_src_ckzti,composite-clock‡auxclk1_src_ck¹ ú!auxclk1_ck@314zti,divider-clock ‡auxclk1_ck¹!±Óµú/auxclk2_src_gate_ck@318z ti,composite-no-wait-gate-clock‡auxclk2_src_gate_ck¹±µú"auxclk2_src_mux_ck@318zti,composite-mux-clock‡auxclk2_src_mux_ck ¹±µú#auxclk2_src_ckzti,composite-clock‡auxclk2_src_ck¹"#ú$auxclk2_ck@318zti,divider-clock ‡auxclk2_ck¹$±Óµú0auxclk3_src_gate_ck@31cz ti,composite-no-wait-gate-clock‡auxclk3_src_gate_ck¹±µú%auxclk3_src_mux_ck@31czti,composite-mux-clock‡auxclk3_src_mux_ck ¹±µú&auxclk3_src_ckzti,composite-clock‡auxclk3_src_ck¹%&ú'auxclk3_ck@31czti,divider-clock ‡auxclk3_ck¹'±Óµú1auxclk4_src_gate_ck@320z ti,composite-no-wait-gate-clock‡auxclk4_src_gate_ck¹±µ ú(auxclk4_src_mux_ck@320zti,composite-mux-clock‡auxclk4_src_mux_ck ¹±µ ú)auxclk4_src_ckzti,composite-clock‡auxclk4_src_ck¹()ú*auxclk4_ck@320zti,divider-clock ‡auxclk4_ck¹*±Óµ ú2auxclk5_src_gate_ck@324z ti,composite-no-wait-gate-clock‡auxclk5_src_gate_ck¹±µ$ú+auxclk5_src_mux_ck@324zti,composite-mux-clock‡auxclk5_src_mux_ck ¹±µ$ú,auxclk5_src_ckzti,composite-clock‡auxclk5_src_ck¹+,ú-auxclk5_ck@324zti,divider-clock ‡auxclk5_ck¹-±Óµ$ú3auxclkreq0_ck@210z ti,mux-clock‡auxclkreq0_ck¹./0123±µauxclkreq1_ck@214z ti,mux-clock‡auxclkreq1_ck¹./0123±µauxclkreq2_ck@218z ti,mux-clock‡auxclkreq2_ck¹./0123±µauxclkreq3_ck@21cz ti,mux-clock‡auxclkreq3_ck¹./0123±µauxclkreq4_ck@220z ti,mux-clock‡auxclkreq4_ck¹./0123±µ auxclkreq5_ck@224z ti,mux-clock‡auxclkreq5_ck¹./0123±µ$clockdomainstarget-module@c000ti,sysc-omap4ti,syscµÀÀ brevsyscl+ [Àscm@c000ti,omap4-scm-wkupµÀsegment@10000simple-pm-bus+x[@@PP€€ÀÀÐÐààððtarget-module@0ti,sysc-omap2ti,syscµbrevsyscsyss l¹   Àfckdbclk+ [gpio@0ti,omap4-gpioµ B%7Gtarget-module@4000ti,sysc-omap2ti,syscµ@@@brevsyscsyss "l ¹ Àfck+ [@wdt@0ti,omap4-wdtti,omap3-wdtµ€ BPtarget-module@8000ti,sysc-omap2-timerti,syscµ€€€brevsyscsyss ' l ¹ Àfck+ [€Sgtimer@0ti,omap3430-timerµ€¹ Àfcktimer_sys_ck B%r  ‘target-module@c000ti,sysc-omap2ti,syscµÀÀÀbrevsyscsyss ' l ¹ XÀfck+ [Àkeypad@0ti,omap4-keypadµ€ Bxbmputarget-module@e000ti,sysc-omap4ti,syscµàà brevsyscl+ [àpinmux@40 ti,omap4-padconfpinctrl-singleµ@8+¨·Õÿtwl6030-wkup-pinsòússegment@20000simple-pm-bus+„[``    00@@PPpp€€target-module@0ti,sysc disabled+ [target-module@2000ti,sysc disabled+ [ target-module@4000ti,sysc disabled+ [@target-module@6000ti,sysc disabled+0[`p €0interconnect@4a000000ti,omap4-l4-cfgsimple-pm-busM4 ¹5ÀfckµJJJ baplaia0+T[JJJJ J (J(0J0segment@0simple-pm-bus+ü[ 00@@PP``ppÀÀ€€@  00€€   ``ppàà @@PPtarget-module@2000ti,sysc-omap4ti,syscµ   brevsyscl+ [ scm@0ti,omap4-scm-coresimple-busµ+ [scm_conf@0sysconµ+ú…control-phy@300ti,control-phy-usb2µbpowerúgcontrol-phy@33cti,control-phy-otghsµ<�botghs_controlúetarget-module@4000ti,sysc-omap4ti,syscµ@brev+ [@cm1@0ti,omap4-cm1simple-busµ + [ clocks+extalt_clkin_ckz fixed-clock‡extalt_clkin_ck „DÀpad_clks_src_ckz fixed-clock‡pad_clks_src_ck ·ú6pad_clks_ck@108zti,gate-clock ‡pad_clks_ck¹6±µpad_slimbus_core_clks_ckz fixed-clock‡pad_slimbus_core_clks_ck ·secure_32k_clk_src_ckz fixed-clock‡secure_32k_clk_src_ck €slimbus_src_clkz fixed-clock‡slimbus_src_clk ·ú7slimbus_clk@108zti,gate-clock ‡slimbus_clk¹7± µsys_32k_ckz fixed-clock ‡sys_32k_ck €úvirt_12000000_ckz fixed-clock‡virt_12000000_ck ·ú virt_13000000_ckz fixed-clock‡virt_13000000_ck Æ]@ú virt_16800000_ckz fixed-clock‡virt_16800000_ck Yúvirt_19200000_ckz fixed-clock‡virt_19200000_ck $øúvirt_26000000_ckz fixed-clock‡virt_26000000_ck Œº€úvirt_27000000_ckz fixed-clock‡virt_27000000_ck ›üÀúvirt_38400000_ckz fixed-clock‡virt_38400000_ck Iðútie_low_clock_ckz fixed-clock‡tie_low_clock_ck utmi_phy_clkout_ckz fixed-clock‡utmi_phy_clkout_ck “‡xclk60mhsp1_ckz fixed-clock‡xclk60mhsp1_ck “‡ú`xclk60mhsp2_ckz fixed-clock‡xclk60mhsp2_ck “‡úaxclk60motg_ckz fixed-clock‡xclk60motg_ck “‡dpll_abe_ck@1e0zti,omap4-dpll-m4xen-clock ‡dpll_abe_ck¹89µàäìèú:dpll_abe_x2_ck@1f0zti,omap4-dpll-x2-clock‡dpll_abe_x2_ck¹:µðú;dpll_abe_m2x2_ck@1f0zti,divider-clock‡dpll_abe_m2x2_ck¹;Óµðš/ú<�abe_24m_fclkzfixed-factor-clock ‡abe_24m_fclk¹<�¾Éabe_clk@108zti,divider-clock‡abe_clk¹<�ÓµFdpll_abe_m3x2_ck@1f4zti,divider-clock‡dpll_abe_m3x2_ck¹;Óµôš/ú=core_hsd_byp_clk_mux_ck@12cz ti,mux-clock‡core_hsd_byp_clk_mux_ck¹=±µ,ú>dpll_core_ck@120zti,omap4-dpll-core-clock ‡dpll_core_ck¹>µ $,(ú?dpll_core_x2_ckzti,omap4-dpll-x2-clock‡dpll_core_x2_ck¹?ú@dpll_core_m6x2_ck@140zti,divider-clock‡dpll_core_m6x2_ck¹@Óµ@š/dpll_core_m2_ck@130zti,divider-clock‡dpll_core_m2_ck¹?Óµ0š/úAddrphy_ckzfixed-factor-clock ‡ddrphy_ck¹A¾Édpll_core_m5x2_ck@13czti,divider-clock‡dpll_core_m5x2_ck¹@Óµ<�š/úBdiv_core_ck@100zti,divider-clock ‡div_core_ck¹BµÓúMdiv_iva_hs_clk@1dczti,divider-clock‡div_iva_hs_clk¹BÓµÜFúFdiv_mpu_hs_clk@19czti,divider-clock‡div_mpu_hs_clk¹BÓµœFúLdpll_core_m4x2_ck@138zti,divider-clock‡dpll_core_m4x2_ck¹@Óµ8š/úCdll_clk_div_ckzfixed-factor-clock‡dll_clk_div_ck¹C¾Édpll_abe_m2_ck@1f0zti,divider-clock‡dpll_abe_m2_ck¹:ÓµðšúPdpll_core_m3x2_gate_ck@134z ti,composite-no-wait-gate-clock‡dpll_core_m3x2_gate_ck¹@±µ4úDdpll_core_m3x2_div_ck@134zti,composite-divider-clock‡dpll_core_m3x2_div_ck¹@Óµ4šúEdpll_core_m3x2_ckzti,composite-clock‡dpll_core_m3x2_ck¹DEúdpll_core_m7x2_ck@144zti,divider-clock‡dpll_core_m7x2_ck¹@ÓµDš/iva_hsd_byp_clk_mux_ck@1acz ti,mux-clock‡iva_hsd_byp_clk_mux_ck¹F±µ¬úGdpll_iva_ck@1a0zti,omap4-dpll-clock ‡dpll_iva_ck¹Gµ ¤¬¨H\7€üúHdpll_iva_x2_ckzti,omap4-dpll-x2-clock‡dpll_iva_x2_ck¹HúIdpll_iva_m4x2_ck@1b8zti,divider-clock‡dpll_iva_m4x2_ck¹IÓµ¸š/J\À~úJdpll_iva_m5x2_ck@1bczti,divider-clock‡dpll_iva_m5x2_ck¹IÓµ¼š/K\Ü] úKdpll_mpu_ck@160zti,omap4-dpll-clock ‡dpll_mpu_ck¹Lµ`dlhúdpll_mpu_m2_ck@170zti,divider-clock‡dpll_mpu_m2_ck¹Óµpš/per_hs_clk_div_ckzfixed-factor-clock‡per_hs_clk_div_ck¹=¾ÉúQusb_hs_clk_div_ckzfixed-factor-clock‡usb_hs_clk_div_ck¹=¾ÉúWl3_div_ck@100zti,divider-clock ‡l3_div_ck¹M±ÓµúNl4_div_ck@100zti,divider-clock ‡l4_div_ck¹N±Óµlp_clk_div_ckzfixed-factor-clock‡lp_clk_div_ck¹<�¾Éúmpu_periphclkzfixed-factor-clock‡mpu_periphclk¹¾Éúocp_abe_iclk@528zti,divider-clock ‡ocp_abe_iclk ¹O±µ(Þper_abe_24m_fclkzfixed-factor-clock‡per_abe_24m_fclk¹P¾Édummy_ckz fixed-clock ‡dummy_ck clockdomainsmpuss_cm@300 ti,omap4-cm ‡mpuss_cmµ+ [clk@20 ti,clkctrl‡mpuss_clkctrlµ zú}tesla_cm@400 ti,omap4-cm ‡tesla_cmµ+ [clk@20 ti,clkctrl‡tesla_clkctrlµ zúbabe_cm@500 ti,omap4-cm‡abe_cmµ+ [clk@20 ti,clkctrl ‡abe_clkctrlµ lzúOtarget-module@8000ti,sysc-omap4ti,syscµ€brev+ [€ cm2@0ti,omap4-cm2simple-busµ + [ clocks+per_hsd_byp_clk_mux_ck@14cz ti,mux-clock‡per_hsd_byp_clk_mux_ck¹Q±µLúRdpll_per_ck@140zti,omap4-dpll-clock ‡dpll_per_ck¹Rµ@DLHúSdpll_per_m2_ck@150zti,divider-clock‡dpll_per_m2_ck¹SÓµPšú[dpll_per_x2_ck@150zti,omap4-dpll-x2-clock‡dpll_per_x2_ck¹SµPúTdpll_per_m2x2_ck@150zti,divider-clock‡dpll_per_m2x2_ck¹TÓµPš/úZdpll_per_m3x2_gate_ck@154z ti,composite-no-wait-gate-clock‡dpll_per_m3x2_gate_ck¹T±µTúUdpll_per_m3x2_div_ck@154zti,composite-divider-clock‡dpll_per_m3x2_div_ck¹TÓµTšúVdpll_per_m3x2_ckzti,composite-clock‡dpll_per_m3x2_ck¹UVúdpll_per_m4x2_ck@158zti,divider-clock‡dpll_per_m4x2_ck¹TÓµXš/údpll_per_m5x2_ck@15czti,divider-clock‡dpll_per_m5x2_ck¹TÓµ\š/dpll_per_m6x2_ck@160zti,divider-clock‡dpll_per_m6x2_ck¹TÓµ`š/úYdpll_per_m7x2_ck@164zti,divider-clock‡dpll_per_m7x2_ck¹TÓµdš/údpll_usb_ck@180zti,omap4-dpll-j-type-clock ‡dpll_usb_ck¹Wµ€„ŒˆúXdpll_usb_clkdcoldo_ck@1b4zti,fixed-factor-clock‡dpll_usb_clkdcoldo_ck¹Xqµ´~/dpll_usb_m2_ck@190zti,divider-clock‡dpll_usb_m2_ck¹XÓµš/ú\ducati_clk_mux_ck@100z ti,mux-clock‡ducati_clk_mux_ck¹MYµfunc_12m_fclkzfixed-factor-clock‡func_12m_fclk¹Z¾Éfunc_24m_clkzfixed-factor-clock ‡func_24m_clk¹[¾Éfunc_24mc_fclkzfixed-factor-clock‡func_24mc_fclk¹Z¾Éfunc_48m_fclk@108zti,divider-clock‡func_48m_fclk¹ZµÞfunc_48mc_fclkzfixed-factor-clock‡func_48mc_fclk¹Z¾Éfunc_64m_fclk@108zti,divider-clock‡func_64m_fclk¹µÞfunc_96m_fclk@108zti,divider-clock‡func_96m_fclk¹ZµÞinit_60m_fclk@104zti,divider-clock‡init_60m_fclk¹\µÞú_per_abe_nc_fclk@108zti,divider-clock‡per_abe_nc_fclk¹PµÓusb_phy_cm_clk32k@640zti,gate-clock‡usb_phy_cm_clk32k¹±µ@úhclockdomainsl3_init_clkdmti,clockdomain‡l3_init_clkdm¹Xl4_ao_cm@600 ti,omap4-cm ‡l4_ao_cmµ+ [clk@20 ti,clkctrl‡l4_ao_clkctrlµ zújl3_1_cm@700 ti,omap4-cm‡l3_1_cmµ+ [clk@20 ti,clkctrl ‡l3_1_clkctrlµ zúl3_2_cm@800 ti,omap4-cm‡l3_2_cmµ+ [clk@20 ti,clkctrl ‡l3_2_clkctrlµ zúducati_cm@900 ti,omap4-cm ‡ducati_cmµ + [ clk@20 ti,clkctrl‡ducati_clkctrlµ zúƒl3_dma_cm@a00 ti,omap4-cm ‡l3_dma_cmµ + [ clk@20 ti,clkctrl‡l3_dma_clkctrlµ zú]l3_emif_cm@b00 ti,omap4-cm ‡l3_emif_cmµ + [ clk@20 ti,clkctrl‡l3_emif_clkctrlµ zú„d2d_cm@c00 ti,omap4-cm‡d2d_cmµ + [ clk@20 ti,clkctrl ‡d2d_clkctrlµ zúil4_cfg_cm@d00 ti,omap4-cm ‡l4_cfg_cmµ + [ clk@20 ti,clkctrl‡l4_cfg_clkctrlµ zú5l3_instr_cm@e00 ti,omap4-cm ‡l3_instr_cmµ+ [clk@20 ti,clkctrl‡l3_instr_clkctrlµ $zú ivahd_cm@f00 ti,omap4-cm ‡ivahd_cmµ+ [clk@20 ti,clkctrl‡ivahd_clkctrlµ zú‘iss_cm@1000 ti,omap4-cm‡iss_cmµ+ [clk@20 ti,clkctrl ‡iss_clkctrlµ zúll3_dss_cm@1100 ti,omap4-cm ‡l3_dss_cmµ+ [clk@20 ti,clkctrl‡l3_dss_clkctrlµ zúl3_gfx_cm@1200 ti,omap4-cm ‡l3_gfx_cmµ+ [clk@20 ti,clkctrl‡l3_gfx_clkctrlµ zúŒl3_init_cm@1300 ti,omap4-cm ‡l3_init_cmµ+ [clk@20 ti,clkctrl‡l3_init_clkctrlµ Äzú^clock@1400 ti,omap4-cm ‡l4_per_cmµ+ [clock@20 ti,clkctrl‡l4_per_clkctrlµ Dzúmclock@1a0 ti,clkctrl‡l4_secure_clkctrlµ <�zúvtarget-module@56000ti,sysc-omap2ti,syscµ``,`(brevsyscsyss # Œ l ¹]Àfck+ [`dma-controller@0ti,omap4430-sdmati,omap-sdmaµ0B  š¥ ²úwtarget-module@58000ti,sysc-omap2ti,syscµ€€€brevsyscsyss #Œl ¹^Àfck+ [€Phsi@0 ti,omap4-hsiµ@Pbsysgdd ¹^Àhsi_fck BG¿gdd_mpu+ [@hsi-port@2000ti,omap4-hsi-portµ (btxrx BChsi-port@3000ti,omap4-hsi-portµ08btxrx BDtarget-module@5e000ti,sysc disabled+ [à target-module@62000ti,sysc-omap2ti,syscµ   brevsyscsyss  l ¹^HÀfck+ [ usbhstll@0 ti,usbhs-tllµ BNtarget-module@64000ti,sysc-omap4ti,syscµ@@@brevsyscsyss Œl ¹^8Àfck+ [@usbhshost@0ti,usbhs-hostµ+ [ ¹_`a3Àrefclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2ohci@800ti,ohci-omap3µ BLÏehci@c00 ti,ehci-omapµ  BMtarget-module@66000ti,sysc-omap2ti,syscµ```brevsyscsyss  l ¹bÀfckMcçcîrstctrl+ [`mmu@0ti,omap4-iommuµ Búú†segment@80000simple-pm-bus+[    ° °À ÀÐ Ðà à@@PP``pp` `p pÐ Ðà à    ° °À ÀÐ Ðà àtarget-module@29000ti,sysc disabled+ [target-module@2b000ti,sysc-omap2ti,syscµ´´´brevsyscsyss  Œl ¹^@Àfck+ [°usb_otg_hs@0ti,omap4-musbµÿB\]¿mcdmadd usb2-phy)1 :eFdefaultTf^mr2target-module@2d000ti,sysc-omap2ti,syscµÐÐÐbrevsyscsyss  l ¹^ÀÀfck+ [Ðocp2scp@0ti,omap-ocp2scpµ+ [usb2phy@80 ti,omap-usb2µ€X:g¹hÀwkupclkxúdtarget-module@36000ti,sysc-omap2ti,syscµ```brevsyscsyss l ¹iÀfck+ [`target-module@4d000ti,sysc-omap2ti,syscµÐÐÐbrevsyscsyss l ¹iÀfck+ [Ðtarget-module@59000ti,sysc-omap4-srti,syscµ8bsysc l ¹jÀfck+ [smartreflex@0ti,omap4-smartreflex-mpuµ€ Btarget-module@5b000ti,sysc-omap4-srti,syscµ°8bsysc l ¹jÀfck+ [°smartreflex@0ti,omap4-smartreflex-ivaµ€ Bftarget-module@5d000ti,sysc-omap4-srti,syscµÐ8bsysc l ¹jÀfck+ [Ðsmartreflex@0ti,omap4-smartreflex-coreµ€ Btarget-module@60000ti,sysc disabled+ [target-module@74000ti,sysc-omap4ti,syscµ@@ brevsysc  l ¹5Àfck+ [@mailbox@0ti,omap4-mailboxµ Bƒ¡ú‡mbox-ipu ³ ¾úŠmbox-dsp ³ ¾úˆtarget-module@76000ti,sysc-omap2ti,syscµ```brevsyscsyss  l ¹5Àfck+ [`spinlock@0ti,omap4-hwspinlockµÉsegment@100000simple-pm-bus+`[  00€€  °°target-module@0ti,sysc-omap4ti,syscµ brevsyscl+ [pinmux@40 ti,omap4-padconfpinctrl-singleµ@–+¨·ÕÿFdefaultúouart3-pinsòúni2c1-pinsòâäúqi2c2-pinsòæèúui2c3-pinsòêìúpi2c4-pinsòîðú{mmc2-pinsPò  BDúyusb-otg-hs-pinsòTVXúftwl6030-pinsò^Aúromap4_padconf_global@5a0sysconsimple-busµ p+ [ púkpbias_regulator@60ti,pbias-omap4ti,pbias-omapµ`×kpbias_mmc_omap4Þpbias_mmc_omap4íw@-ÆÀúxtarget-module@2000ti,sysc disabled+ [ target-module@8000ti,sysc disabled+ [€target-module@a000ti,sysc-omap4ti,syscµ   brevsysc  Œ l ¹lÀfck+ [ segment@180000simple-pm-bus+segment@200000simple-pm-bus+h[à!àð!ð   ° °@ @P P` `p p ! 0!0À ÀÐ Ð!!`!`p!p@!@P!P€!€!""`"`p"p€"€" " °"°À!ÀÐ!Ðtarget-module@4000ti,sysc disabled+ [@target-module@6000ti,sysc disabled+ [`target-module@a000ti,sysc disabled+ [ target-module@c000ti,sysc disabled+ [Àtarget-module@10000ti,sysc disabled+ [target-module@12000ti,sysc disabled+ [ target-module@14000ti,sysc disabled+ [@target-module@16000ti,sysc disabled+ [`target-module@18000ti,sysc disabled+ [€target-module@1c000ti,sysc disabled+ [Àtarget-module@1e000ti,sysc disabled+ [àtarget-module@20000ti,sysc disabled+ [target-module@26000ti,sysc disabled+ [`target-module@28000ti,sysc disabled+ [€target-module@2a000ti,sysc disabled+ [ segment@280000simple-pm-bus+segment@300000simple-pm-bus+„[042@@2@ `2`p2p€2€23 2  À2À@target-module@0ti,sysc disabled+x[@@@ ``pp€€   ÀÀ@interconnect@48000000ti,omap4-l4-persimple-pm-busM ¹m Àfck0µHHHHHHbaplaia0ia1ia2ia3+[H H segment@0simple-pm-bus+ä[  00@@PP``ppààððPP``pp€€  °°ÀÀÐÐàà  °°ÀÀÐÐààðð  00 ` ` p p``pp€€``pp€€    € €       ° ° À À Ð Ð à à ð ð  @ @ ` ` € €@ À À Ð Ð à à  0 0 @ @ P P € €       ° °    P P ` `  0 0 P Ptarget-module@20000ti,sysc-omap2ti,syscµPTXbrevsyscsyss l ¹m0Àfck+ [serial@0ti,omap4-uartµ BJ ÜlFdefaultTn.Jotarget-module@32000ti,sysc-omap2-timerti,syscµ   brevsyscsyss ' l ¹mÀfck+ [ timer@0ti,omap3430-timerµ€¹mÀfcktimer_sys_ck B&target-module@34000ti,sysc-omap4-timerti,syscµ@@ brevsysc l ¹m Àfck+ [@timer@0ti,omap4430-timerµ€¹m Àfcktimer_sys_ck B'target-module@36000ti,sysc-omap4-timerti,syscµ`` brevsysc l ¹m(Àfck+ [`timer@0ti,omap4430-timerµ€¹m(Àfcktimer_sys_ck B(target-module@3e000ti,sysc-omap4-timerti,syscµàà brevsysc l ¹m0Àfck+ [àtimer@0ti,omap4430-timerµ€¹m0Àfcktimer_sys_ck B-Btarget-module@40000ti,sysc disabled+ [target-module@55000ti,sysc-omap2ti,syscµPPQbrevsyscsyss l¹m@m@ Àfckdbclk+ [Pgpio@0ti,omap4-gpioµ B7Gtarget-module@57000ti,sysc-omap2ti,syscµppqbrevsyscsyss l¹mHmH Àfckdbclk+ [pgpio@0ti,omap4-gpioµ B7Gú’target-module@59000ti,sysc-omap2ti,syscµ‘brevsyscsyss l¹mPmP Àfckdbclk+ [gpio@0ti,omap4-gpioµ B 7Gtarget-module@5b000ti,sysc-omap2ti,syscµ°°±brevsyscsyss l¹mXmX Àfckdbclk+ [°gpio@0ti,omap4-gpioµ B!7Gtarget-module@5d000ti,sysc-omap2ti,syscµÐÐÑbrevsyscsyss l¹m`m` Àfckdbclk+ [Ðgpio@0ti,omap4-gpioµ B"7Gtarget-module@60000ti,sysc-omap2ti,syscµbrevsyscsyss l ¹mÀfck+ [i2c@0 ti,omap4-i2cµ B=+FdefaultTp €target-module@6a000ti,sysc-omap2ti,syscµ P T Xbrevsyscsyss l ¹m Àfck+ [ serial@0ti,omap4-uartµ BH Ültarget-module@6c000ti,sysc-omap2ti,syscµÀPÀTÀXbrevsyscsyss l ¹m(Àfck+ [Àserial@0ti,omap4-uartµ BI Ültarget-module@6e000ti,sysc-omap2ti,syscµàPàTàXbrevsyscsyss l ¹m8Àfck+ [àserial@0ti,omap4-uartµ BF Ültarget-module@70000ti,sysc-omap2ti,syscµbrevsyscsyss l ¹m€Àfck+ [i2c@0 ti,omap4-i2cµ B8+FdefaultTq €twl@48µH B ti,twl6030FdefaultTrspowerti,twl6030-powerOrtcti,twl4030-rtcB regulator-vaux1ti,twl6030-vaux1íB@-ÆÀúzregulator-vaux2ti,twl6030-vaux2íO€*¹€regulator-vaux3ti,twl6030-vaux3íB@-ÆÀregulator-vmmcti,twl6030-vmmcíO€-ÆÀregulator-vppti,twl6030-vppíw@&% regulator-vusimti,twl6030-vusimíO€,@ regulator-vdacti,twl6030-vdacregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxiojregulator-vusbti,twl6030-vusbútregulator-v1v8ti,twl6030-v1v8jregulator-v2v1ti,twl6030-v2v1jusb-comparatorti,twl6030-usbB ~tpwmti,twl6030-pwm‰ú–pwmledti,twl6030-pwmled‰gpadcti,twl6030-gpadcB”target-module@72000ti,sysc-omap2ti,syscµ   brevsyscsyss l ¹mˆÀfck+ [ i2c@0 ti,omap4-i2cµ B9+FdefaultTu €target-module@76000ti,sysc-omap4ti,syscµ`` brevsysc l ¹mÀfck+ [`target-module@78000ti,sysc-omap2ti,syscµ€€€brevsyscsyss  l ¹m8Àfck+ [€elm@0ti,am3352-elmµ  B disabledtarget-module@86000ti,sysc-omap2-timerti,syscµ```brevsyscsyss ' l ¹mÀfck+ [`timer@0ti,omap3430-timerµ€¹mÀfcktimer_sys_ck B.Btarget-module@88000ti,sysc-omap4-timerti,syscµ€€ brevsysc l ¹mÀfck+ [€timer@0ti,omap4430-timerµ€¹mÀfcktimer_sys_ck B/Btarget-module@90000ti,sysc-omap2ti,syscµ à ä brevsysc l ¹v Àfck+ [ rng@0 ti,omap4-rngµ  B4target-module@96000ti,sysc-omap2ti,syscµ `Œbsysc  l ¹mÀÀfck+ [ `mcbsp@0ti,omap4-mcbspµÿbmpu ¹mÀÀfck B¿common¦€µww ºtxrx disabledtarget-module@98000ti,sysc-omap4ti,syscµ € € brevsysc l ¹mÐÀfck+ [ €spi@0ti,omap4-mcspiµ BA+Ä@µw#w$w%w&w'w(w)w* ºtx0rx0tx1rx1tx2rx2tx3rx3target-module@9a000ti,sysc-omap4ti,syscµ     brevsysc l ¹mØÀfck+ [  spi@0ti,omap4-mcspiµ BB+Ä µw+w,w-w.ºtx0rx0tx1rx1target-module@9c000ti,sysc-omap4ti,syscµ À À brevsysc Œl ¹^Àfck+ [ Àmmc@0ti,omap4-hsmmcµ BSÒßµw=w>ºtxrxöx disabledtarget-module@9e000ti,sysc disabled+ [ àtarget-module@a2000ti,sysc disabled+ [ target-module@a4000ti,sysc disabled+[ @ Ptarget-module@a5000ti,sysc-omap2ti,syscµ P0 P4 P8brevsyscsyss l ¹vÀfck+ [ Pdes@0 ti,omap4-desµ  BRµwuwtºtxrxtarget-module@a8000ti,sysc disabled+ [ €@target-module@ad000ti,sysc-omap4ti,syscµ Ð Ð brevsysc Œl ¹mÀfck+ [ Ðmmc@0ti,omap4-hsmmcµ B^ßµwMwNºtxrx disabledtarget-module@b0000ti,sysc disabled+ [ target-module@b2000ti,sysc-omap2ti,syscµ   brevsyscsyss S ¹mhÀfck+ [ 1w@0 ti,omap3-1wµ B:target-module@b4000ti,sysc-omap4ti,syscµ @ @ brevsysc Œl ¹^Àfck+ [ @mmc@0ti,omap4-hsmmcµ BVßµw/w0ºtxrxFdefaultTyz target-module@b8000ti,sysc-omap4ti,syscµ € € brevsysc l ¹màÀfck+ [ €spi@0ti,omap4-mcspiµ B[+ĵwwºtx0rx0target-module@ba000ti,sysc-omap4ti,syscµ     brevsysc l ¹mèÀfck+ [  spi@0ti,omap4-mcspiµ B0+ĵwFwGºtx0rx0target-module@d1000ti,sysc-omap4ti,syscµ   brevsysc Œl ¹mÀfck+ [ mmc@0ti,omap4-hsmmcµ B`ßµw9w:ºtxrx disabledtarget-module@d5000ti,sysc-omap4ti,syscµ P P brevsysc Œl ¹m@Àfck+ [ Pmmc@0ti,omap4-hsmmcµ B;ßµw;w<�ºtxrxsegment@200000simple-pm-bus+[55target-module@150000ti,sysc-omap2ti,syscµbrevsyscsyss l ¹m˜Àfck+ [i2c@0 ti,omap4-i2cµ B>+FdefaultT{ €target-module@48210000ti,sysc-omap4-simpleti,syscM| ¹}Àfck+ [H!mpu ti,omap4-mpu*~interconnect@40100000ti,omap4-l4-abesimple-pm-busµ@@blaapM+[@IIsegment@0simple-pm-bus+0[  00@@PP``pp€€  °°ààðð  00€€  °°ÀÀÐÐààðð      IIIII I I0I0I@I@IPIPI`I`IpIpI€I€III I I°I°IàIàIðIðIIIII I I0I0I€I€III I I°I°IÀIÀIÐIÐIàIàIðIðIIIII I I I I I I I III I target-module@22000ti,sysc-omap2ti,syscµ Œbsysc  l ¹O(Àfck+[ I I mcbsp@0ti,omap4-mcbspµÿI ÿbmpudma ¹O(Àfck B¿common¦€µw!w"ºtxrx disabledtarget-module@24000ti,sysc-omap2ti,syscµ@Œbsysc  l ¹O0Àfck+[@I@I@mcbsp@0ti,omap4-mcbspµÿI@ÿbmpudma ¹O0Àfck B¿common¦€µwwºtxrx disabledtarget-module@26000ti,sysc-omap2ti,syscµ`Œbsysc  l ¹O8Àfck+[`I`I`mcbsp@0ti,omap4-mcbspµÿI`ÿbmpudma ¹O8Àfck B¿common¦€µwwºtxrx disabledtarget-module@28000ti,sysc-mcaspti,syscµ€€ brevsysc l ¹O Àfck+0[€I€I€  I I mcasp@0ti,omap4-mcasp-audioµ I bmpudat Bm¿txµwºtx ¹O Àfck/7 disabledtarget-module@2e000ti,sysc-omap4ti,syscµàà brevsysc l ¹OÀfck+[àIàIàdmic@0ti,omap4-dmicµIàbmpudma BrµwCºup_link disabledtarget-module@30000ti,sysc-omap2ti,syscµbrevsyscsyss "l ¹OhÀfck+[IIwdt@0ti,omap4-wdtti,omap3-wdtµ€ BPtarget-module@32000ti,sysc-omap4ti,syscµ   brevsysc l ¹OÀfck+[ I I  disabledmcpdm@0ti,omap4-mcpdmµI bmpudma BpµwAwBºup_linkdn_linktarget-module@38000ti,sysc-omap4-timerti,syscµ€€ brevsysc l ¹OHÀfck+[€I€I€timer@0ti,omap4430-timerµ€I€€¹OH€Àfcktimer_sys_ck B)Btarget-module@3a000ti,sysc-omap4-timerti,syscµ   brevsysc l ¹OPÀfck+[ I I timer@0ti,omap4430-timerµ€I €¹OP€Àfcktimer_sys_ck B*Btarget-module@3c000ti,sysc-omap4-timerti,syscµÀÀ brevsysc l ¹OXÀfck+[ÀIÀIÀtimer@0ti,omap4430-timerµ€IÀ€¹OX€Àfcktimer_sys_ck B+Btarget-module@3e000ti,sysc-omap4-timerti,syscµàà brevsysc l ¹O`Àfck+[àIàIàtimer@0ti,omap4430-timerµ€Ià€¹O`€Àfcktimer_sys_ck B,BBtarget-module@80000ti,sysc disabled+[IItarget-module@a0000ti,sysc disabled+[ I I target-module@c0000ti,sysc disabled+[ I I target-module@f1000ti,sysc-omap4ti,syscµ brevsyscŒ l ¹OÀfck+[IItarget-module@50000000ti,sysc-omap2ti,syscµPPPbrevsyscsyss lO ¹Àfck+[PP@gpmc@50000000ti,omap4430-gpmcµP+ Bµwºrxtxbn¹NÀfck7Gtarget-module@52000000ti,sysc-omap4ti,syscµRR brevsysc ŒlM ¹lÀfck+ [Rtarget-module@54000000ti,sysc-omap4-simpleti,syscM‚ ¹Àfck+ [Tpmuarm,cortex-a9-pmutarget-module@55082000ti,sysc-omap2ti,syscµU U U brevsyscsyss l  ¹ƒÀfckç4îrstctrl [U +mmu@0ti,omap4-iommuµ Bdú€ú‰target-module@4012c000ti,sysc-omap4ti,syscµ@À@À brevsysc l ¹O@Àfck+[@ÀIÀIÀtarget-module@4e000000ti,sysc-omap2ti,syscµNN brevsysc l [N+dmm@0 ti,omap4-dmmµ Bqtarget-module@4c000000ti,sysc-omap4-simpleti,syscµLbrev ¹„Àfckg+ [Lemif@0 ti,emif-4dµ Bn–Ÿ¶Ëtarget-module@4d000000ti,sysc-omap4-simpleti,syscµMbrev ¹„Àfckg+ [Memif@0 ti,emif-4dµ Bo–Ÿ¶Ëdsp ti,omap4-dsp Þ…é†çc ¹bðomap4-dsp-fw.xe64Tþ‡ˆ disabledipu@55020000 ti,omap4-ipuµUbl2ramé‰ç44 ¹ƒðomap4-ipu-fw.xem3þ‡Š disabledtarget-module@4b501000ti,sysc-omap2ti,syscµKP€KP„KPˆbrevsyscsyss l ¹vÀfck+ [KPaes@0 ti,omap4-aesµ  BUµwownºtxrxtarget-module@4b701000ti,sysc-omap2ti,syscµKp€Kp„Kpˆbrevsyscsyss l ¹vÀfck+ [Kpaes@0 ti,omap4-aesµ  B@µwrwqºtxrxtarget-module@4b100000ti,sysc-omap3-shamti,syscµKKKbrevsyscsyss  l ¹v(Àfck+ [Ksham@0ti,omap4-shamµ B3µwwºrxregulator-abb-mpu ti,abb-v2Þabb_mpu+€¹2/okayµJ0{ÐJ0`bbase-addressint-addressx?£èO€èû1Èregulator-abb-iva ti,abb-v2Þabb_iva+€¹2/ disabledµJ0{ØJ0`bbase-addressint-addresstarget-module@56000000ti,sysc-omap4ti,syscµVþVþ brevsyscŒlM‹ ¹ŒÀfck+ [VŒ\O€‘gpu@0#ti,omap4430-gpuimg,powervr-sgx540µ Btarget-module@58000000ti,sysc-omap2ti,syscµXX brevsyssMŽ0¹   Àfckhdmi_clksys_clktv_clk+ [Xdss@0 ti,omap4-dssµ€ disabled ¹Àfck+ [target-module@1000ti,sysc-omap2ti,syscµbrevsyscsyss l Œ ¹  Àfcksys_clk+ [dispc@0ti,omap4-dispcµ B ¹Àfcktarget-module@2000ti,sysc-omap2ti,syscµ   brevsyscsyss l ¹  Àfcksys_clk+ [ encoder@0µ disabled¹NÀfckicktarget-module@3000ti,sysc-omap2ti,syscµ0brev ¹ Àsys_clk+ [0encoder@0ti,omap4-vencµ disabled ¹ Àfcktarget-module@4000ti,sysc-omap2ti,syscµ@@@brevsyscsyss l + [@encoder@0 ti,omap4-dsiµ@ bprotophypll B5 disabled¹  Àfcksys_clk+target-module@5000ti,sysc-omap2ti,syscµPPPbrevsyscsyss l + [Pencoder@0 ti,omap4-dsiµ@ bprotophypll BT disabled¹  Àfcksys_clk+target-module@6000ti,sysc-omap4ti,syscµ`` brevsyscl ¹  Àfckdss_clk+ [` encoder@0ti,omap4-hdmi µbwppllphycore Be disabled¹   Àfcksys_clkµwL ºaudio_txtarget-module@5a000000ti,sysc-omap4ti,syscµZ¤Z¤ brevsysc Œ lMçîrstctrl ¹‘Àfck+[ZZ[[iva ti,ivahdbandgap@4a002260µJ"`J#,ti,omap4430-bandgap K’Qú“thermal-zonescpu_thermalgú}è‹“›N tripscpu_alert¨† ´ÐŸpassiveú”cpu_crit¨èH´Ð Ÿcriticalcooling-mapsmap0¿” Ä•ÿÿÿÿÿÿÿÿmemory@80000000˜memoryµ€ led-controller pwm-ledsled-1Ógreen Ù–w5”Þled-2Óorange Ù–w5”Þ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3mmc0mmc1mmc2mmc3mmc4serial0serial1serial2serial3rproc0rproc1device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-points#cooling-cellsphandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptspower-domainsrangesreg-namesti,sysc-sidle#clock-cellsclock-output-namesti,index-starts-at-oneti,bit-shiftclock-multclock-divti,max-divti,dividers#power-domain-cells#reset-cellsti,sysc-maskti,syss-maskti,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parents#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsstatusclock-frequencyti,autoidle-shiftti,invert-autoidle-bitti,index-power-of-twoassigned-clock-ratesti,clock-divti,clock-multti,sysc-midle#dma-cellsdma-channelsdma-requestsinterrupt-namesremote-wakeup-connectedresetsreset-names#iommu-cellsusb-phyphysphy-namesmultipointnum-epsram-bitsctrl-modulepinctrl-namespinctrl-0interface-typemodepower#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,sysc-delay-usinterrupts-extendedti,timer-pwmti,system-power-controllerregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,buffer-sizedmasdma-namesti,spi-num-csti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplyti,non-removablebus-widthsramop-modeserial-dirti,timer-dspti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsti,iommu-bus-err-backphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertti,bootregiommusfirmware-namemboxesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infogpios#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-devicelabelpwmsmax-brightness