Ð þí_{8[D(7[ ,Merrii A80 Optimus Board'2merrii,a80-optimusallwinner,sun9i-a80aliases=/soc@20000/ethernet@830000G/soc@20000/serial@7000000O/soc@20000/serial@7001000cpuscpu@02arm,cortex-a7Wcpuct·„allwinner,sun9i-a80-smp’cpu@12arm,cortex-a7Wcpuct·„allwinner,sun9i-a80-smp’cpu@22arm,cortex-a7Wcpuct·„allwinner,sun9i-a80-smp’cpu@32arm,cortex-a7Wcpuct·„allwinner,sun9i-a80-smp’cpu@1002arm,cortex-a15Wcpuct¨€„allwinner,sun9i-a80-smp’cpu@1012arm,cortex-a15Wcpuct¨€„allwinner,sun9i-a80-smp’cpu@1022arm,cortex-a15Wcpuct¨€„allwinner,sun9i-a80-smp’cpu@1032arm,cortex-a15Wcpuct¨€„allwinner,sun9i-a80-smp’timer2arm,armv7-timer0–   tn6¡clocksÅ clk-24MÌ 2fixed-clocktn6Ùosc24Mìclk-32kÌ2fixed-factor-clockôþÙosc32k ìmii-phy-tx-clkÌ 2fixed-clockt}x@ Ùmii_phy_txìgmac-int-tx-clkÌ 2fixed-clocktsY@ Ùgmac_int_txìclk@800030Ì2allwinner,sun7i-a20-gmac-clk’€0 Ùgmac_txìclk@80014102allwinner,sun9i-a80-cpus-clk’Ì   Ùcpusì clk-ahbs2fixed-factor-clockÌôþ Ùahbsì clk@800141c2allwinner,sun8i-a23-apb0-clk’Ì Ùapbsì clk@8001428#2allwinner,sun9i-a80-apbs-gates-clk’(Ì 8 ŠÙapbs_pioapbs_irapbs_timerapbs_rsbapbs_uartapbs_1wireapbs_i2c0apbs_i2c1apbs_ps2_0apbs_ps2_1apbs_dmaapbs_i2s0apbs_i2s1apbs_twdì>clk@8001450’PÌ2allwinner,sun4i-a10-mod0-clk Ùr_1wireclk@8001454’TÌ2allwinner,sun4i-a10-mod0-clk Ùr_irì?display-engine#2allwinner,sun9i-a80-display-engine  2disabledsoc@20000 2simple-busÅ sram@20000 2mmio-sram’ Åsmp-sram@10002allwinner,sun9i-a80-smp-sram’ethernet@8300002allwinner,sun7i-a20-gmac’ƒT –R9macirq  aIstmmacethallwinner_gmac_txU  \stmmacethhq‚2okay™default§± ¼rgmii-idÅmdio2snps,dwmac-mdioethernet-phy@1’ìusb@a00000&2allwinner,sun9i-a80-ehcigeneric-ehci’  –H UÐÕusb2okayusb@a00400&2allwinner,sun9i-a80-ohcigeneric-ohci’  –I UÐÕusb2okayphy@a008002allwinner,sun9i-a80-usb-phy’  IphyU\phy2okayßÅìusb@a01000&2allwinner,sun9i-a80-ehcigeneric-ehci’  –J UÐÕusb 2disabledphy@a018002allwinner,sun9i-a80-usb-phy’   Iphyhsic_12Mhsic_480MU \phyhsic 2disabledßêhsicÅìusb@a02000&2allwinner,sun9i-a80-ehcigeneric-ehci’   –L UÐÕusb2okayusb@a02400&2allwinner,sun9i-a80-ohcigeneric-ohci’ $ –M UÐÕusb2okayphy@a028002allwinner,sun9i-a80-usb-phy’ (   Iphyhsic_12Mhsic_480MU \phyhsic2okayßÅìclock@a080002allwinner,sun9i-a80-usb-clks’ €  ` IbushoscÌóìcpucfg@17000002allwinner,sun9i-a80-cpucfg’pcrypto@1c020002allwinner,sun9i-a80-crypto’À  –PU  S .Ibusmodmmc@1c0f0002allwinner,sun9i-a80-mmc’Àð   ! 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#address-cells#size-cellsinterrupt-parentmodelcompatibleethernet0serial0serial1device_typecci-control-portclock-frequencyenable-methodreginterruptsarm,cpu-registers-not-fw-configuredranges#clock-cellsclock-output-namesphandleclock-divclock-multclocksclock-indicesallwinner,pipelinesstatusinterrupt-namesclock-namesresetsreset-namessnps,pblsnps,fixed-burstsnps,force_sf_dma_modepinctrl-namespinctrl-0phy-handlephy-modephy-supplyphysphy-names#phy-cellsphy_type#reset-cellsvmmc-supplybus-widthcd-gpiosvqmmc-supplymmc-pwrseqnon-removablecap-mmc-hw-resetinterrupt-controller#interrupt-cellsinterface-typeremote-endpointgpio-controller#gpio-cellsvcc-pa-supplyvcc-pb-supplyvcc-pc-supplyvcc-pd-supplyvcc-pe-supplyvcc-pf-supplyvcc-pg-supplyvcc-ph-supplypinsfunctiondrive-strengthbias-pull-upreg-shiftreg-io-widthvcc-pl-supplyvcc-pm-supplyregulator-always-onregulator-min-microvoltregulator-max-microvoltregulator-namebldoin-supplyregulator-enable-ramp-delaystdout-pathlabelenable-active-highgpioreset-gpios