Ð þíc¯8^ô(»^¼  ,HAOYU Electronics Marsboard A20(2haoyu,a20-marsboardallwinner,sun7i-a20aliases=/soc/ethernet@1c50000G/soc/serial@1c28000chosen OVserial0:115200n8framebuffer-lcd0-hdmi02allwinner,simple-framebuffersimple-framebufferbde_be0-lcd0-hdmi8u8<�>›Œ¤ |disabledframebuffer-lcd002allwinner,simple-framebuffersimple-framebuffer bde_be0-lcd0(u8>•Œ |disabledframebuffer-lcd0-tve002allwinner,simple-framebuffersimple-framebufferbde_be0-lcd0-tve08u68>›‡Œ |disabledcpus cpu@02arm,cortex-a7ƒcpuu“¹°8¡¦\À ê€\À /Ö ü€O€€ÈàÂÀB@2€B@²ÁÌcpu@12arm,cortex-a7ƒcpuu“¹°8¡¦\À ê€\À /Ö ü€O€€ÈàÂÀB@2€B@²Ìthermal-zonescpu-thermalÔúêèøcooling-mapsmap0 ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtripscpu-alert0$ø(ЊpassiveÌcpu-crit† (Ð Šcriticalreserved-memory Odefault-pool2shared-dma-pool38@ENtimer2arm,armv7-timer0`   pmu2arm,cortex-a7-pmu`xyclocks Oclk-24Mk 2fixed-clockxn6ˆosc24MÌ"clk-32kk 2fixed-clockx€ˆosc32kÌ#clk-mii-phy-txk 2fixed-clockx}x@ ˆmii_phy_txÌclk-gmac-int-txk 2fixed-clockxsY@ ˆgmac_int_txÌ clk@1c20164k2allwinner,sun7i-a20-gmac-clkÂdu ˆgmac_txÌ*display-engine#2allwinner,sun7i-a20-display-engine› |okaysoc 2simple-bus Osystem-control@1c00000F2allwinner,sun7i-a20-system-controlallwinner,sun4i-a10-system-controlÀ0 Osram@0 2mmio-sramÀ  OÀsram-section@8000>2allwinner,sun7i-a20-sram-a3-a4allwinner,sun4i-a10-sram-a3-a4€@ |disabledÌ sram@10000 2mmio-sram  Osram-section@062allwinner,sun7i-a20-sram-dallwinner,sun4i-a10-sram-d|okayÌsram@1d00000 2mmio-sramÐ   OÐ sram-section@082allwinner,sun7i-a20-sram-c1allwinner,sun4i-a10-sram-c1Ìinterrupt-controller@1c000302allwinner,sun7i-a20-sc-nmi¯ÄÀ0  `Ì&dma-controller@1c020002allwinner,sun4i-a10-dmaÀ  `u ÕÌ nand-controller@1c030002allwinner,sun4i-a10-nandÀ0 `%u'`àahbmod ì ñrxtx |disabled spi@1c050002allwinner,sun4i-a10-spiÀP ` u,pàahbmodì  ñrxtx |disabled ûspi@1c060002allwinner,sun4i-a10-spiÀ` ` u-qàahbmodì  ñrxtx |disabled ûcsi@1c090002allwinner,sun7i-a20-csi0À `*u:—ƒ àbusispram |disabledethernet@1c0b0002allwinner,sun4i-a10-emacÀ° `7u*  |disabledmdio@1c0b0802allwinner,sun4i-a10-mdioÀ°€ |disabled lcd-controller@1c0c00032allwinner,sun7i-a20-tcon0allwinner,sun7i-a20-tconÀÀ `,  lcdlvdsu8•›àahbtcon-ch0tcon-ch1ˆtcon0-pixel-clockk ì ports port@0 endpoint@0$Ì8endpoint@1$Ì4port@1 endpoint@1$4Ìlcd-controller@1c0d00032allwinner,sun7i-a20-tcon1allwinner,sun7i-a20-tconÀÐ `- lcdu9–àahbtcon-ch0tcon-ch1ˆtcon1-pixel-clockk ì ports port@0 endpoint@0$Ì9endpoint@1$Ì5port@1 endpoint@1$4Ìvideo-codec@1c0e000!2allwinner,sun7i-a20-video-engineÀàu4¡‚ àahbmodram `5 mmc@1c0f0002allwinner,sun7i-a20-mmcÀð u"bcdàahbmmcoutputsample ` KdefaultY|okay coy mmc@1c100002allwinner,sun7i-a20-mmcÁ u#efgàahbmmcoutputsample `! |disabled mmc@1c110002allwinner,sun7i-a20-mmcÁ u$hijàahbmmcoutputsample `"KdefaultY |disabled mmc@1c120002allwinner,sun7i-a20-mmcÁ  u%klmàahbmmcoutputsample `#KdefaultY |disabled usb@1c130002allwinner,sun4i-a10-musbÁ0u `&‚mc’—usb¡ ¨otg|okayphy@1c13400°2allwinner,sun7i-a20-usb-phyÁ4ÁHÁÈ»phy_ctrlpmu1pmu2u}àusb_phy!usb0_resetusb1_resetusb2_reset|okayÅ×èÌusb@1c14000&2allwinner,sun7i-a20-ehcigeneric-ehciÁ@ `'u’—usb|okayusb@1c14400&2allwinner,sun7i-a20-ohcigeneric-ohciÁD `@u{’—usb|okaycrypto-engine@1c1500062allwinner,sun7i-a20-cryptoallwinner,sun4i-a10-cryptoÁP `Vuoàahbmodhdmi@1c1600032allwinner,sun7i-a20-hdmiallwinner,sun5i-a10s-hdmiÁ` `: u<�¤ àahbmodpll-0pll-1$ì   ñddc-txddc-rxaudio-tx|okayports port@0 endpoint@0$Ìendpoint@1$Ìport@1endpoint$ Ì:spi@1c170002allwinner,sun4i-a10-spiÁp ` u.ràahbmodì  ñrxtx |disabled ûsata@1c180002allwinner,sun4i-a10-ahciÁ€ `8u1z|okayù!usb@1c1c000&2allwinner,sun7i-a20-ehcigeneric-ehciÁÀ `(u’—usb|okayusb@1c1c400&2allwinner,sun7i-a20-ohcigeneric-ohciÁÄ `Au|’—usb|okaycsi@1c1d00022allwinner,sun7i-a20-csi1allwinner,sun4i-a10-csi1ÁÐ `+u;„àbusram |disabledspi@1c1f0002allwinner,sun4i-a10-spiÁð `2u/àahbmodì  ñrxtx |disabled ûclock@1c200002allwinner,sun7i-a20-ccuÂu"# àhosclosckÌpinctrl@1c208002allwinner,sun7i-a20-pinctrlÂ `uJ"#àapbhosclosc¯Ä$Ìgmac-mii-pinsK0PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA165gmacÌ+i2c0-pins0PB0PB15i2c0Ì%i2c1-pins 0PB18PB195i2c1Ì'i2c2-pins 0PB20PB215i2c2Ì(i2c3-pins0PI0PI15i2c3Ì)mmc0-pins0PF0PF1PF2PF3PF4PF55mmc0>MÌmmc2-pins0PC6PC7PC8PC9PC10PC115mmc2>MÌmmc3-pins0PI4PI5PI6PI7PI8PI95mmc3>MÌuart0-pb-pins 0PB22PB235uart0Ì$gmac-txerr-pin0PA175gmacÌ,timer@1c20c002allwinner,sun4i-a10-timer H`CDu"watchdog@1c20c902allwinner,sun4i-a10-wdt  `u"rtc@1c20d002allwinner,sun7i-a20-rtc  `pwm@1c20e002allwinner,sun7i-a20-pwmÂ u"Z |disabledspdif@1c21000e2allwinner,sun4i-a10-spdifÂ ` uFx àapbspdifì  ñrxtx |disabledir@1c218002allwinner,sun4i-a10-iruKtàapbir `Â@ |disabledir@1c21c002allwinner,sun4i-a10-iruLuàapbir `Â@ |disabledi2s@1c22000e2allwinner,sun4i-a10-i2s  `WuI€àapbmodì  ñrxtx |disabledi2s@1c22400e2allwinner,sun4i-a10-i2sÂ$ `uGvàapbmodì  ñrxtx |disabledlradc@1c228002allwinner,sun4i-a10-lradc-keysÂ( ` |disabledcodec@1c22c00e2allwinner,sun7i-a20-codecÂ,@ `uE  àapbcodecì  ñrxtx|okayeeprom@1c238002allwinner,sun7i-a20-sidÂ8i2s@1c24400e2allwinner,sun4i-a10-i2sÂD `ZuMàapbmodì  ñrxtx |disabledrtp@1c250002allwinner,sun5i-a13-tsÂP `vÌserial@1c280002snps,dw-apb-uart€ `Œ–uX|okayKdefaultY$serial@1c284002snps,dw-apb-uart„ `Œ–uY |disabledserial@1c288002snps,dw-apb-uartˆ `Œ–uZ |disabledserial@1c28c002snps,dw-apb-uartÂŒ `Œ–u[ |disabledserial@1c290002snps,dw-apb-uart `Œ–u\ |disabledserial@1c294002snps,dw-apb-uart” `Œ–u] |disabledserial@1c298002snps,dw-apb-uart˜ `Œ–u^ |disabledserial@1c29c002snps,dw-apb-uartÂœ `Œ–u_ |disabledps2@1c2a0002allwinner,sun4i-a10-ps2  `>uU |disabledps2@1c2a4002allwinner,sun4i-a10-ps2¤ `?uV |disabledi2c@1c2ac0002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c¬ `uOKdefaultY%|okay pmic@344&`2x-powers,axp209¯Äac-power 2x-powers,axp202-ac-power-supply|okayadc2x-powers,axp209-adc£Ì;gpio2x-powers,axp209-gpio$battery-power%2x-powers,axp209-battery-power-supply |disabledregulatorsµÜdcdc2Èvdd-cpu×ëB@ Ìdcdc3 Èvdd-int-dll×ëB@\Àldo1×ëÖ Ö Èvdd-rtcldo2Èavcc×ë-ÆÀ-ÆÀldo3Èldo3ldo4Èldo4ldo5Èldo5 |disabledusb-power!2x-powers,axp202-usb-power-supply |disabledi2c@1c2b00002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c° `uPKdefaultY' |disabled i2c@1c2b40002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c´ ` uQKdefaultY( |disabled i2c@1c2b80002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2c¸ `XuRKdefaultY) |disabled can@1c2bc0002allwinner,sun7i-a20-canallwinner,sun4i-a10-can¼ `uS |disabledi2c@1c2c00002allwinner,sun7i-a20-i2callwinner,sun4i-a10-i2cÂÀ `YuW |disabled gpu@1c40000&2allwinner,sun7i-a20-maliarm,mali-400ÄT`EFGHJKI#‚gpgpmmupp0ppmmu0pp1ppmmu1pmuuD¥ àbuscore¥+ã`ethernet@1c500002allwinner,sun7i-a20-gmacÅ `U‚macirq uB*àstmmacethallwinner_gmac_tx@IZ|okayKdefaultY+,q-|miimdio2snps,dwmac-mdio ethernet-phy@0Ì-hstimer@1c600002allwinner,sun7i-a20-hstimerÆ0`QRSTu3interrupt-controller@1c81000 2arm,gic-400 ÈÈ È@ È` ¯Ä ` Ìdisplay-frontend@1e00000%2allwinner,sun7i-a20-display-frontendà `/u@’‹ àahbmodramÌ ports port@1 endpoint@0$.Ì6endpoint@1$/Ì2display-frontend@1e20000%2allwinner,sun7i-a20-display-frontendâ `0uA“Š àahbmodramÌ ports port@1 endpoint@0$0Ì7endpoint@1$1Ì3display-backend@1e40000$2allwinner,sun7i-a20-display-backendä `0u?‘ àahbmodramports port@0 endpoint@0$2Ì/endpoint@1$3Ì1port@1 endpoint@0$4Ìendpoint@1$5Ìdisplay-backend@1e60000$2allwinner,sun7i-a20-display-backendæ `/u>Œ àahbmodramports port@0 endpoint@0$6Ì.endpoint@1$7Ì0port@1 endpoint@0$8Ìendpoint@1$9Ìahci-5v2regulator-fixedÈahci-5vëLK@LK@…—ª|okayÌ!usb0-vbus2regulator-fixed Èusb0-vbusëLK@LK@—ª  |disabledusb1-vbus2regulator-fixed Èusb1-vbusëLK@LK@…—ª|okayÌusb2-vbus2regulator-fixed Èusb2-vbusëLK@LK@…—ª|okayÌvcc3v02regulator-fixedÈvcc3v0ë-ÆÀ-ÆÀvcc3v32regulator-fixedÈvcc3v3ë2Z 2Z Ìvcc5v02regulator-fixedÈvcc5v0ëLK@LK@hdmi-connector2hdmi-connectorŠaportendpoint$:Ì pmic-temp 2iio-hwmon¯; interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0serial0rangesstdout-pathallwinner,pipelineclocksstatusdevice_typeregclock-latencyoperating-points#cooling-cellscpu-supplyphandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresissizealloc-rangesreusablelinux,cma-defaultinterrupts#clock-cellsclock-frequencyclock-output-namesallwinner,pipelinesinterrupt-controller#interrupt-cells#dma-cellsclock-namesdmasdma-namesnum-csresetsallwinner,sramreset-namesremote-endpointallwinner,tcon-channelpinctrl-namespinctrl-0vmmc-supplybus-widthcd-gpiosinterrupt-namesphysphy-namesextcondr_mode#phy-cellsreg-namesusb0_id_det-gpiosusb1_vbus-supplyusb2_vbus-supplytarget-supply#reset-cellsgpio-controller#gpio-cellspinsfunctiondrive-strengthbias-pull-up#pwm-cells#sound-dai-cells#thermal-sensor-cellsreg-shiftreg-io-width#io-channel-cellsx-powers,dcdc-freqregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltassigned-clocksassigned-clock-ratessnps,pblsnps,fixed-burstsnps,force_sf_dma_modephy-handlephy-moderegulator-boot-onenable-active-highgpioio-channels