Ð þíU38M˜(›M`Sedgeble,neural-compute-module-2-ioedgeble,neural-compute-module-2rockchip,rv1126&7Edgeble Neu2 IO Boardaliases=/i2c@ff3f0000B/i2c@ff400000G/serial@ff560000O/serial@ff410000W/serial@ff570000_/serial@ff580000g/serial@ff590000o/serial@ff5a0000w/mmc@ffc50000cpuscpu@f00|cpuarm,cortex-a7ˆŒpsciš¡¬cpu@f01|cpuarm,cortex-a7ˆŒpsciš¬cpu@f02|cpuarm,cortex-a7ˆŒpsciš¬cpu@f03|cpuarm,cortex-a7ˆŒpsciš¬arm-pmuarm,cortex-a7-pmu0´{|}~¿psci arm,psci-1.0“smctimerarm,armv7-timer0´   Òn6display_subsystemrockchip,display-subsystemâoscillator fixed-clockÒn6èxin24mû¬#syscon@fe000000&rockchip,rv1126-grfsysconsimple-mfdˆþ¬"syscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfdˆþ¬io-domains&rockchip,rv1126-pmu-io-voltage-domainokay  + 9 G Uc q qos@fe860000rockchip,rv1126-qossysconˆþ† ¬qos@fe860080rockchip,rv1126-qossysconˆþ†€ ¬qos@fe860200rockchip,rv1126-qossysconˆþ† ¬qos@fe86c000rockchip,rv1126-qossysconˆþ†À ¬qos@fe8a0000rockchip,rv1126-qossysconˆþŠ ¬qos@fe8a0080rockchip,rv1126-qossysconˆþŠ€ ¬qos@fe8a0100rockchip,rv1126-qossysconˆþŠ ¬qos@fe8a0180rockchip,rv1126-qossysconˆþŠ€ ¬interrupt-controller@feff0000 arm,gic-400¢ ˆþÿþÿ þÿ@ þÿ`  ´ ¬power-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfdˆÿ>power-controller!rockchip,rv1126-power-controller³¬0power-domain@15ˆ8šèréuêëv dzpower-domain@16ˆšæodzpower-domain@10ˆ Pš®ÙZ¯Úš°Û[dzi2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2cˆÿ? ´Îš ! Ûi2cpclkçdefaultõokayÒ€pmic@20rockchip,rk809ˆ &´ ûèrk808-clkout1rk808-clkout2çdefaultõÿ .:FR^jv‚ Ž¬(regulatorsDCDC_REG1 švdd_npu_vepu©½Ïæ ëþ~ðqregulator-state-mem+DCDC_REG2švdd_arm©½Ïæ þ™pq¬regulator-state-mem+DCDC_REG3švcc_ddr©½Ïregulator-state-memDDCDC_REG4 švcc3v3_sys©½Ïæ2Z þ2Z ¬ regulator-state-memD\2Z DCDC_REG5 švcc_buck5©½æ!‘Àþ!‘À¬regulator-state-memD\!‘ÀLDO_REG1švcc_0v8©½æ 5þ 5regulator-state-mem+LDO_REG2 švcc1v8_pmu©½æw@þw@¬ regulator-state-memD\w@LDO_REG3 švcc0v8_pmu©½æ 5þ 5regulator-state-memD\ 5LDO_REG4švcc_1v8©½æw@þw@¬ regulator-state-memD\w@LDO_REG5 švcc_dovdd½æw@þw@¬regulator-state-mem+LDO_REG6 švcc_dvddæO€þO€regulator-state-mem+LDO_REG7 švcc_avddæ*¹€þ*¹€regulator-state-mem+LDO_REG8 švccio_sd©½æw@þ2Z ¬ regulator-state-mem+LDO_REG9 švcc3v3_sd©½æ2Z þ2Z regulator-state-mem+SWITCH_REG1švcc_5v0SWITCH_REG2švcc_3v3©½¬5i2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2cˆÿ@ ´Îš " Ûi2cpclkçdefaultõ disabledserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uartˆÿA ´ Òn6š  Ûbaudclkapb_pclkx}txrxçdefaultõ ‡‘ disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwmˆÿC  Ûpwmpclkš#çdefaultõ!ž disabledclock-controller@ff480000rockchip,rv1126-pmucruˆÿHÎ"û©¬clock-controller@ff490000rockchip,rv1126-cruˆÿIš#Ûxin24mÎ"û©¬dma-controller@ff4e0000arm,pl330arm,primecellˆÿN@´¶Áš¡ Ûapb_pclk¬pwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwmˆÿU0 Ûpwmpclkš'õ$çdefaultžokayserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uartˆÿV ´ Òn6šúÛbaudclkapb_pclkx}txrxçdefault õ%&'‡‘okaybluetoothqcom,qca9377-btš( Ø)å„€çdefaultõ*ï ü serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uartˆÿW ´Òn6šûÛbaudclkapb_pclkx }txrxçdefaultõ+‡‘okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uartˆÿX ´Òn6šüÛbaudclkapb_pclkx  }txrxçdefaultõ,‡‘ disabledserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uartˆÿY ´Òn6šýÛbaudclkapb_pclkx  }txrxçdefaultõ-‡‘ disabledserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uartˆÿZ ´Òn6š þÛbaudclkapb_pclkx}txrxçdefaultõ.‡‘ disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradcˆÿ^ ´( š, Ûsaradcapb_pclk; "saradc-apbokay. timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timerˆÿf  ´š - Ûpclktimervop@ffb00000rockchip,rv1126-vopˆÿ°ÿ°  ´;Ûaclk_vopdclk_vophclk_vopš¯šÚ "axiahbdclk†‡ˆ:/A0  disabledport¬endpoint@0ˆendpoint@1ˆiommu@ffb00f00rockchip,iommuˆÿ° ´; Ûaclkifaceš¯ÚOA0  disabled¬/ethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20aˆÿÄ@´_`\macirqeth_wake_irqÎ"@š~ˆˆ¿ˆ‰TÛstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_ref¾ "stmmacethl}†1–2©3okay¼~ˆŠÌ}ƒ ãsY@}x@øinput4rgmii5çdefaultõ6789$*-mdiosnps,dwmac-mdioethernet-phy@04ethernet-phy-id001c.c916ethernet-phy-ieee802.3-c22ˆçdefaultõ:6N F†  X¬4stmmac-axi-configdt„¬1rx-queues-configŽ¬2queue0tx-queues-config¤¬3queue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshcˆÿÅ@ ´N šèrstÛbiuciuciu-driveciu-sampleºÅ ëÂA0okayÓÝçdefault õ;<�=ëZ 5 mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshcˆÿÆ@ ´L šälmnÛbiuciuciu-driveciu-sampleºÅ ëÂokayÓ"4EÈçdefaultõ>?@AëZWdq mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshcˆÿÇ@ ´M šæopqÛbiuciuciu-driveciu-sampleºÅõáA0okayÓ4Œ¢BÝçdefault õCDEëZq  spi@ffc90000 rockchip,sfcˆÿÉ@ ´P¼vãÄ´Ûclk_sfchclk_sfcšvêA0okayçdefaultõFflash@0jedec,spi-norˆ­úð€¿Ðpinctrlrockchip,rv1126-pinctrlÎ"áîgpio@ff460000rockchip,gpio-bankˆÿF ´"š&õ¢¬gpio@ff620000rockchip,gpio-bankˆÿb ´#š(õ¢¬Ogpio@ff630000rockchip,gpio-bankˆÿc ´$š)õ¢gpio@ff640000rockchip,gpio-bankˆÿd ´%š*õ¢¬)gpio@ff650000rockchip,gpio-bankˆÿe ´&š +õ¢pcfg-pull-up¬Jpcfg-pull-down¬Ipcfg-pull-none-¬Gpcfg-pull-none-drv-level-3-:¬Lpcfg-pull-up-drv-level-2:¬Hpcfg-pull-none-drv-level-0-smt-:I¬Kclk_out_ethernetclk-out-ethernetm1-pins^G¬9emmcemmc-bus8€^HHHHHHHH¬;emmc-clk^H¬=emmc-cmd^H¬<�fspifspi-pins`^IJJJJJ¬Fi2c0i2c0-xfer ^ K K¬i2c2i2c2-xfer ^KK¬pwm2pwm2m0-pins^G¬!pwm11pwm11m0-pins^G¬$rgmiirgmiim1-miim ^GG¬6rgmiim1-bus2`^ GG GLLL¬7rgmiim1-bus4`^GGGLLL¬8sdmmc0sdmmc0-bus4@^HHHH¬@sdmmc0-clk^H¬>sdmmc0-cmd^ H¬?sdmmc0-det^G¬Asdmmc1sdmmc1-bus4@^ H HHH¬Esdmmc1-clk^ H¬Csdmmc1-cmd^ H¬Duart0uart0-xfer ^JJ¬%uart0-ctsn^G¬&uart0-rtsn^G¬'uart1uart1m0-xfer ^JJ¬ uart2uart2m1-xfer ^JJ¬+uart3uart3m0-xfer ^JJ¬,uart4uart4m0-xfer ^JJ¬-uart5uart5m0-xfer ^JJ¬.btbt-enable^G¬*flashflash-vol-sel^ G¬Mpmicpmic-int-l^ J¬wifiwifi-enable-h^G¬Netherneteth-phy-rst^I¬:vccio-flash-regulatorregulator-fixedl  çdefaultõM švccio_flash©½æw@þw@„5¬ pwrseq-sdiommc-pwrseq-simpleš( Ûext_clockçdefaultõN XO¬Bchosenserial2:1500000n8vcc12v-dcin-regulatorregulator-fixed švcc12v_dcin©½æ·þ·¬Pvcc5v0-sys-regulatorregulator-fixed švcc5v0_sys©½æLK@þLK@„P¬v3v3-sys-regulatorregulator-fixed šv3v3_sys©½æ2Z þ2Z „ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2serial0serial1serial2serial3serial4serial5mmc0device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstenable-gpiosmax-speedvddxo-supplyvddio-supply#io-channel-cellsresetsreset-namesvref-supplyiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplytx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsenable-active-highgpiovin-supplystdout-path