Ð þí¡98—ð( I—¸%amarula,vyasa-rk3288rockchip,rk3288&7Amarula Vyasa-RK3288aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000‚/i2c@ff140000‡/i2c@ff660000Œ/i2c@ff150000‘/i2c@ff160000–/i2c@ff170000›/mmc@ff0f0000¡/mmc@ff0c0000§/mmc@ff0d0000­/mmc@ff0e0000³/serial@ff180000»/serial@ff190000Ã/serial@ff690000Ë/serial@ff1b0000Ó/serial@ff1c0000Û/spi@ff110000à/spi@ff120000å/spi@ff130000arm-pmuarm,cortex-a12-pmu0ê—˜™šõcpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@501#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@502#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@503#cpuarm,cortex-a12/3:N]œ@krrŒ —opp-table-0operating-points-v2Ÿ—opp-126000000ª‚›€± » opp-216000000ª ßæ± » opp-312000000ª˜¾± » opp-408000000ªQ–± » opp-600000000ª#ÃF± » opp-696000000ª)|±~ðopp-816000000ª0£,±B@opp-1008000000ª<ܱopp-1200000000ªG†Œ±Èàopp-1416000000ªTfr±O€opp-1512000000ªZJ±Ö opp-1608000000ª_Ø"±™preserved-memory¿dma-unusable@fe000000/þoscillator fixed-clockÆn6Öxin24mé— timerarm,armv7-timerö0ê   Æn6timer@ff810000rockchip,rk3288-timer/ÿ  êH ka  1pclktimerdisplay-subsystemrockchip,display-subsystem= mmc@ff0c0000rockchip,rk3288-dw-mshcCðÑ€ kÈDrv1biuciuciu-driveciu-sampleQ ê /ÿ @3€\resethokayoy‹œÈ®¹defaultÇ ÑÝmmc@ff0d0000rockchip,rk3288-dw-mshcCðÑ€ kÉEsw1biuciuciu-driveciu-sampleQ ê!/ÿ @3\reset hdisabledmmc@ff0e0000rockchip,rk3288-dw-mshcCðÑ€ kÊFtx1biuciuciu-driveciu-sampleQ ê"/ÿ@3‚\reset hdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcCðÑ€ kËGuy1biuciuciu-driveciu-sampleQ ê#/ÿ@3ƒ\resethokayoyê¹defaultÇÑsaradc@ff100000rockchip,saradc/ÿ ê$økI[1saradcapb_pclk3W \saradc-apb hdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR1spiclkapb_pclk   txrx ê,¹defaultÇ/ÿ hdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS1spiclkapb_pclk  txrx ê-¹defaultÇ /ÿ hdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT1spiclkapb_pclk txrx ê.¹defaultÇ!"#$/ÿ hdisabledi2c@ff140000rockchip,rk3288-i2c/ÿ ê>1i2ckM¹defaultÇ% hdisabledi2c@ff150000rockchip,rk3288-i2c/ÿ ê?1i2ckO¹defaultÇ& hdisabledi2c@ff160000rockchip,rk3288-i2c/ÿ ê@1i2ckP¹defaultÇ' hdisabledi2c@ff170000rockchip,rk3288-i2c/ÿ êA1i2ckQ¹defaultÇ(hokay—qserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê7#kMU1baudclkapb_pclk txrx¹defaultÇ) hdisabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê8#kNV1baudclkapb_pclk txrx¹defaultÇ* hdisabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿi ê9#kOW1baudclkapb_pclk¹defaultÇ+hokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê:#kPX1baudclkapb_pclk txrx¹defaultÇ, hdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê;#kQY1baudclkapb_pclk   txrx¹defaultÇ- hdisableddma-controller@ff250000arm,pl330arm,primecell/ÿ%@ê0;Vk 1apb_pclk—thermal-zonesreserve-thermalm胈‘.cpu-thermalmdƒˆ‘.tripscpu_alert0¡p­Ð*passive—/cpu_alert1¡$ø­Ð*passive—0cpu_crit¡_­Ð *criticalcooling-mapsmap0¸/0½ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1¸00½ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermalmdƒˆ‘.tripsgpu_alert0¡p­Ð*passive—1gpu_crit¡_­Ð *criticalcooling-mapsmap0¸1 ½2ÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadc/ÿ( ê%kHZ1tsadcapb_pclk3Ÿ \tsadc-apb¹initdefaultsleepÇ3Ì4Ö3àö5shokay1—.ethernet@ff290000rockchip,rk3288-gmac/ÿ)êLmacirqeth_wake_irqö58k—fgc˜Ä]M1stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B \stmmacethhokay\—l6ƒinput¹defaultÇ789:;›rgmii¤ º'B@ Ï<�ß0èusb@ff500000 generic-ehci/ÿP êkÂñ=öusbhokayusb@ff520000 generic-ohci/ÿR ê)kÂñ=öusb hdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿT êkÃ1otghostñ> öusb2-phyhokay¹defaultÇ?usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿX êkÁ1otgotg1@€€@@ ñ@ öusb2-phyhokayOAusb@ff5c0000 generic-ehci/ÿ\ êkÄ hdisableddma-controller@ff600000arm,pl330arm,primecell/ÿ`@ê0;VkÁ 1apb_pclk hdisabledi2c@ff650000rockchip,rk3288-i2c/ÿe ê<�1i2ckL¹defaultÇBhokayÆ€pmic@1brockchip,rk808/&CêéÖxin32krk808-clkout2¹defaultÇDE[|ŠF–F¢F®FºFÆFÒÞFêF÷FregulatorsDCDC_REG1vdd_arm q°8™pPd— regulator-state-memvDCDC_REG2vdd_gpu øP8ÐPd—vregulator-state-mem§B@DCDC_REG3vcc_ddrPdregulator-state-memDCDC_REG4vcc_io 2Z 82Z Pd—regulator-state-mem§2Z LDO_REG1vcc_tp 2Z 82Z Pdregulator-state-mem§2Z LDO_REG2 vcc_codec 2Z 82Z Pdregulator-state-memvLDO_REG3vdd_10 B@8B@Pdregulator-state-mem§B@LDO_REG4vcc_gps w@8w@Pdregulator-state-mem§w@LDO_REG5 vccio_sd w@82Z Pd—regulator-state-mem§2Z LDO_REG6 vdd10_lcd B@8B@Pdregulator-state-mem§B@LDO_REG7vcc_18 w@8w@Pd—Zregulator-state-mem§w@LDO_REG8 vcc18_lcd w@8w@Pdregulator-state-mem§w@SWITCH_REG1vcc_sd 2Z 82Z Pd—regulator-state-memSWITCH_REG2vcc_lan 2Z 82Z Pd—;regulator-state-memi2c@ff660000rockchip,rk3288-i2c/ÿf ê=1i2ckN¹defaultÇG hdisabledpwm@ff680000rockchip,rk3288-pwm/ÿhùdefaultÇHk_ hdisabledpwm@ff680010rockchip,rk3288-pwm/ÿhùdefaultÇIk_ hdisabledpwm@ff680020rockchip,rk3288-pwm/ÿh ùdefaultÇJk_ hdisabledpwm@ff680030rockchip,rk3288-pwm/ÿh0ùdefaultÇKk_ hdisabledsram@ff700000 mmio-sram/ÿp€¿ÿp€smp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/ÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/ÿs—power-controller!rockchip,rk3288-power-controllerÎ\hl —^power-domain@9/ ÈkÊÍÈÌÅƾ¿ÔÕÖÙÑÒchgfdehilkj$âLMNOPQRSTÎpower-domain@11/ kÏopâUVÎpower-domain@12/ kÐÜâWÎpower-domain@13/ kÀâXYÎreboot-modesyscon-reboot-modeé”ðRBÃüRBà RBà RBÃsyscon@ff740000rockchip,rk3288-sgrfsyscon/ÿtclock-controller@ff760000rockchip,rk3288-cru/ÿvk 1xin24mö5é&H\ÑÝjÒÞk$3#g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀ—syscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/ÿw—5edp-phyrockchip,rk3288-dp-phykh124mH hdisabled—nio-domains"rockchip,rk3288-io-voltage-domainhokaySZ`juZƒ;‘Ÿ¯»ÉZusbphyrockchip,rk3288-usb-phyhokayusb-phy@320H/ k]1phyclké3… \phy-reset—@usb-phy@334H/4k^1phyclké3ˆ \phy-reset—=usb-phy@348H/Hk_1phyclké3‹ \phy-reset—>watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/ÿ€kp êOhokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/ÿ‹ÕkTÐ 1mclkhclk [tx ê6¹defaultÇ\ö5 hdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ÿ‰Õ ê5kRÎ1i2s_clki2s_hclk [[txrx¹defaultÇ]æ hdisabledcrypto@ff8a0000rockchip,rk3288-crypto/ÿŠ@ ê0 kÇÍ}Á1aclkhclksclkapb_pclk3® \crypto-rstiommu@ff900800rockchip,iommu/ÿ@ êkÊÔ 1aclkiface hdisablediommu@ff914000rockchip,iommu /ÿ‘@ÿ‘P êkÍÕ 1aclkiface( hdisabledrga@ff920000rockchip,rk3288-rga/ÿ’€ êkÈÖj1aclkhclksclkC^ 3ilm \coreaxiahbvop@ff930000rockchip,rk3288-vop /ÿ“œÿ“ êkžÑ1aclk_vopdclk_vophclk_vopC^ 3def \axiahbdclkQ_hokayport— endpoint@0/X`—rendpoint@1/Xa—oendpoint@2/Xb—iendpoint@3/Xc—liommu@ff930300rockchip,iommu/ÿ“ êkÅÑ 1aclkifaceC^ hokay—_vop@ff940000rockchip,rk3288-vop /ÿ”œÿ” êkÆ¿Ò1aclk_vopdclk_vophclk_vopC^ 3°±² \axiahbdclkQdhokayport— endpoint@0/Xe—sendpoint@1/Xf—pendpoint@2/Xg—jendpoint@3/Xh—miommu@ff940300rockchip,iommu/ÿ” êkÆÒ 1aclkifaceC^ hokay—ddsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/ÿ–@ êk~d 1refpclkC^ ö5 hdisabledportsport@0/endpoint@0/Xi—bendpoint@1/Xj—gport@1/lvds@ff96c000rockchip,rk3288-lvds/ÿ–À@kg 1pclk_lvds¹lcdcÇkC^ ö5 hdisabledportsport@0/endpoint@0/Xl—cendpoint@1/Xm—hport@1/dp@ff970000rockchip,rk3288-dp/ÿ—@ êbkic1dppclkñnödpC^ 3o\dpö5 hdisabledportsport@0/endpoint@0/Xo—aendpoint@1/Xp—fport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/ÿ˜# êgkhmn1iahbisfrcecC^ ö5Õhokayhqportsport@0/endpoint@0/Xr—`endpoint@1/Xs—eport@1/video-codec@ff9a0000rockchip,rk3288-vpu/ÿšê   LvepuvdpukÐÜ 1aclkhclkQtC^ iommu@ff9a0800rockchip,iommu/ÿš ê kÐÜ 1aclkifaceC^ —tiommu@ff9c0440rockchip,iommu /ÿœ@@ÿœ€@ êokÏÛ 1aclkiface hdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/ÿ£$ê LjobmmugpukÀ:uNC^ hokaytv—2opp-table-1operating-points-v2—uopp-100000000ªõá±~ðopp-200000000ª ë±~ðopp-300000000ªá£±B@opp-400000000ªׄ±Èàopp-600000000ª#ÃF±Ðqos@ffaa0000rockchip,rk3288-qossyscon/ÿª —Xqos@ffaa0080rockchip,rk3288-qossyscon/ÿª€ —Yqos@ffad0000rockchip,rk3288-qossyscon/ÿ­ —Mqos@ffad0100rockchip,rk3288-qossyscon/ÿ­ —Nqos@ffad0180rockchip,rk3288-qossyscon/ÿ­€ —Oqos@ffad0400rockchip,rk3288-qossyscon/ÿ­ —Pqos@ffad0480rockchip,rk3288-qossyscon/ÿ­€ —Qqos@ffad0500rockchip,rk3288-qossyscon/ÿ­ —Lqos@ffad0800rockchip,rk3288-qossyscon/ÿ­ —Rqos@ffad0880rockchip,rk3288-qossyscon/ÿ­€ —Sqos@ffad0900rockchip,rk3288-qossyscon/ÿ­ —Tqos@ffae0000rockchip,rk3288-qossyscon/ÿ® —Wqos@ffaf0000rockchip,rk3288-qossyscon/ÿ¯ —Uqos@ffaf0080rockchip,rk3288-qossyscon/ÿ¯€ —Vdma-controller@ffb20000arm,pl330arm,primecell/ÿ²@ê0;VkÁ 1apb_pclk—[efuse@ffb40000rockchip,rk3288-efuse/ÿ´ kq 1pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400€•@/ÿÀÿÀ ÿÀ@ ÿÀ`  ê —pinctrlrockchip,rk3288-pinctrlö5¿gpio@ff750000rockchip,gpio-bank/ÿu êQk@¦¶€•—Cgpio@ff780000rockchip,gpio-bank/ÿx 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsdmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizevbus-supplyrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathvin-supplyenable-active-high