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þíV8Q¨(`Qp$rockchip,rk3128-evbrockchip,rk3128+!7Rockchip RK3128 Evaluation boardaliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000/mmc@1021c000arm-pmuarm,cortex-a7-pmu0†LMNO‘cpus+¤rockchip,rk3036-smpcpu@f00²cpuarm,cortex-a7¾Âœ@Ð×Þòcpu@f01²cpuarm,cortex-a7¾×Þcpu@f02²cpuarm,cortex-a7¾×Þcpu@f03²cpuarm,cortex-a7¾×Þopp-table-0operating-points-v2 opp-216000000ßæ~ð~ð7Èopp-408000000Q–~ð~ð7Èopp-600000000#ÃF~ð~ð7Èopp-696000000)|à˜à˜7Èopp-8160000000£,g8g87È)opp-1008000000<ÜO€O€7Èopp-1200000000G†Œ7È7È7Èdisplay-subsystemrockchip,display-subsystem5 ;disabledopp-table-1operating-points-v2 opp-200000000ëÂà˜à˜Ðopp-300000000á£Ðopp-400000000ׄŒ0Œ0Ðopp-480000000œ8ÐÐÐtimerarm,armv7-timer0†
Bfn6oscillatorfixed-clockfn6vxin24m‰"sram@10080000
mmio-sram¾ +– smp-sram@0rockchip,rk3066-smp-sram¾gpu@10090000"rockchip,rk3128-maliarm,mali-400¾ H†gpgpmmupp0ppmmu0pp1ppmmu1ÐÕÕ buscoreÞ ×x¹
;disabledsyscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd¾
power-controller!rockchip,rk3128-power-controllerÇ+
power-domain@1¾ˆÐÆÖ¿ÑÇÔÌÏEÍÓÀÁÒÕ¾zÛ
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âaxiahbdclk¹
;disabledport+endpoint@0¾î(qos@1012d000rockchip,rk3128-qossyscon¾Ð qos@1012e000rockchip,rk3128-qossyscon¾à qos@1012f000rockchip,rk3128-qossyscon¾ð qos@1012f080rockchip,rk3128-qossyscon¾ð€ qos@1012f100rockchip,rk3128-qossyscon¾ñ qos@1012f180rockchip,rk3128-qossyscon¾ñ€
qos@1012f200rockchip,rk3128-qossyscon¾ò interrupt-controller@10139000arm,cortex-a7-gic ¾ À à † þusb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2¾†
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generic-ehci¾†ÐÙ\ausb;okayusb@101e0000
generic-ohci¾† ÐÙ\ausb;okaymmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!@@† ÐÈDrvbiuciuciu-driveciu-samplew
|rx-tx†‘ðÑ€×Qâreset ;disabledmmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!€@† ÐÉEswbiuciuciu-driveciu-samplew|rx-tx†‘ðÑ€×Râreset ;disabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!À@† ÐËGuybiuciuciu-driveciu-samplew|rx-tx†‘ðÑ€×Sâreset;okayŸ©default·nand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfc¾P@†ÐÅCahbnfc©default · ! ;disabledclock-controller@20000000rockchip,rk3128-cru¾ Ð"xin24mÁ#‰ÎÛë#g¸€syscon@20008000&rockchip,rk3128-grfsysconsimple-mfd¾ €+#usb2phy@17crockchip,rk3128-usb2phy¾|ÐŽphyclkvusb480m_phyÛš$‰;okay$host-port†5
linestate;okayotg-port$†#34otg-bvalidotg-idlinestate;okayhdmi@20034000rockchip,rk3128-inno-hdmi¾ @@†-ÐG¾ pclkref©default·%&'¹
;disabledports+port@0¾endpointî(port@1¾timer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer¾ @ †ÐaUpclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer¾ @ †ÐaVpclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer¾ @@ †;ÐaWpclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer¾ @` †<�ÐaXpclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer¾ @€ †=ÐaYpclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer¾ @ †>ÐaZpclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt¾ À†"Ð? ;disabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Ð^©default·)" ;disabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Ð^©default·*" ;disabledpwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Ð^©default·+" ;disabledpwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ 0Ð^©default·," ;disabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ `†i2cÐM©default·-+;okayrtc@51haoyu,hym8563¾Q‰vxin32ki2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ †i2cÐN©default·.+ ;disabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ à†i2cÐO©default·/+ ;disabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart¾ †fn6ÐMUbaudclkapb_pclkw|txrx©default·012-: ;disabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart¾ @†fn6ÐNVbaudclkapb_pclkw|txrx©default·3-: ;disabledserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart¾ €†fn6ÐOWbaudclkapb_pclkw|txrx©default·4-: ;disabledsaradc@2006c000rockchip,saradc¾ À†Ð[>saradcapb_pclk×Wâsaradc-apbD ;disabledi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ †i2cÐL©default·5+ ;disabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi¾ @†ÐARspiclkapb_pclkw |txrx©default·6789:+ ;disableddma-controller@20078000arm,pl330arm,primecell¾ €@†VqРapb_pclkˆethernet@2008c000rockchip,rk3128-gmac¾ À@†89macirqeth_wake_irq8Ð~‚€ÔoMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac×8
âstmmacethÁ#“¡ ;disabledmdiosnps,dwmac-mdio+pinctrlrockchip,rk3128-pinctrlÁ#+–gpio@2007c000rockchip,gpio-bank¾ À†$Ð@¯¿þ=gpio@20080000rockchip,gpio-bank¾ †%ÐA¯¿þgpio@20084000rockchip,gpio-bank¾ @†&ÐB¯¿þ?gpio@20088000rockchip,gpio-bank¾ €†'ÐC¯¿þpcfg-pull-defaultË<�pcfg-pull-noneá;emmcemmc-clkî;emmc-cmdî<�emmc-cmd1î<�emmc-pwrî<�emmc-bus1î<�emmc-bus4@î<�<�<�<�emmc-bus8€î<�<�<�<�<�<�<�<�gmacrgmii-pinsðî<� <�<�<�
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;;i2s1-bus`î;;;;;;lcdclcdc-dclkî;lcdc-denî;lcdc-hsyncî ;lcdc-vsyncî
;lcdc-rgb24àî;
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vcc5v0_otgLK@4LK@vcc5v0-host-regulatorregulator-fixed?©default·@
vcc5v0_hostLLK@4LK@ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2mmc0interruptsinterrupt-affinityenable-methoddevice_typeregclock-latencyclocksresetsoperating-points-v2#cooling-cellsphandleopp-sharedopp-hzopp-microvoltopp-suspendportsstatusarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domains#power-domain-cellspm_qosreset-namesremote-endpointinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesvbus-supplydmasdma-namesfifo-depthmax-frequencybus-widthpinctrl-namespinctrl-0rockchip,grf#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathgpioregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on