Ð þíV8Q¨(`Qp$rockchip,rk3128-evbrockchip,rk3128 +!7Rockchip RK3128 Evaluation boardaliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000/mmc@1021c000arm-pmuarm,cortex-a7-pmu0†LMNO‘cpus+¤rockchip,rk3036-smpcpu@f00²cpuarm,cortex-a7¾Âœ@Ð×Þòcpu@f01²cpuarm,cortex-a7¾×Þcpu@f02²cpuarm,cortex-a7¾×Þcpu@f03²cpuarm,cortex-a7¾×Þopp-table-0operating-points-v2 opp-216000000 ßæ ~ð~ð7Èopp-408000000Q– ~ð~ð7Èopp-600000000#ÃF ~ð~ð7Èopp-696000000)| à˜à˜7Èopp-8160000000£, g8g87È)opp-1008000000<Ü O€O€7Èopp-1200000000G†Œ 7È7È7Èdisplay-subsystemrockchip,display-subsystem5 ;disabledopp-table-1operating-points-v2 opp-200000000 ë à˜à˜Ðopp-300000000ᣠÐopp-400000000ׄ Œ0Œ0Ðopp-480000000œ8 ÐÐÐtimerarm,armv7-timer0†   Bfn6oscillator fixed-clockfn6vxin24m‰"sram@10080000 mmio-sram¾ + – smp-sram@0rockchip,rk3066-smp-sram¾gpu@10090000"rockchip,rk3128-maliarm,mali-400¾ H†gpgpmmupp0ppmmu0pp1ppmmu1ÐÕÕ ­buscoreÞ ×x¹  ;disabledsyscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd¾ power-controller!rockchip,rk3128-power-controllerÇ+ power-domain@1¾ˆÐÆÖ¿ÑÇÔÌÏEÍÓÀÁÒÕ¾zÛ Çpower-domain@2¾(ÐÅÎÄ͆ÛÇpower-domain@3¾ÐÕÛÇvop@1010e000rockchip,rk3126-vop¾à † Ð̾ϭaclk_vopdclk_vophclk_vop×def âaxiahbdclk¹  ;disabledport+endpoint@0¾î(qos@1012d000rockchip,rk3128-qossyscon¾Ð qos@1012e000rockchip,rk3128-qossyscon¾à qos@1012f000rockchip,rk3128-qossyscon¾ð qos@1012f080rockchip,rk3128-qossyscon¾ð€  qos@1012f100rockchip,rk3128-qossyscon¾ñ  qos@1012f180rockchip,rk3128-qossyscon¾ñ€  qos@1012f200rockchip,rk3128-qossyscon¾ò interrupt-controller@10139000arm,cortex-a7-gic ¾ À à  † þusb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2¾ † ÐÚ­otg$otg,>M€€@ \ ausb2-phy;okaykusb@101c0000 generic-ehci¾ † ÐÙ\ausb;okayusb@101e0000 generic-ohci¾ † ÐÙ\ausb;okaymmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!@@ † ÐÈDrv­biuciuciu-driveciu-samplew |rx-tx†‘ðÑ€×Qâreset ;disabledmmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!€@ † ÐÉEsw­biuciuciu-driveciu-samplew |rx-tx†‘ðÑ€×Râreset ;disabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc¾!À@ † ÐËGuy­biuciuciu-driveciu-samplew |rx-tx†‘ðÑ€×Sâreset;okayŸ©default ·nand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfc¾P@ †ÐÅC­ahbnfc©default · ! ;disabledclock-controller@20000000rockchip,rk3128-cru¾ Ð"­xin24mÁ#‰ÎÛë#g¸€syscon@20008000&rockchip,rk3128-grfsysconsimple-mfd¾ €+#usb2phy@17crockchip,rk3128-usb2phy¾| ÐŽ­phyclk vusb480m_phyÛš$‰;okay$host-port †5 linestate;okayotg-port$†#34otg-bvalidotg-idlinestate;okayhdmi@20034000rockchip,rk3128-inno-hdmi¾ @@ †-ÐG¾ ­pclkref©default ·%&'¹  ;disabledports+port@0¾endpointî(port@1¾timer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer¾ @  †ÐaU ­pclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer¾ @  †ÐaV ­pclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer¾ @@  †;ÐaW ­pclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer¾ @`  †<�ÐaX ­pclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer¾ @€  †=ÐaY ­pclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer¾ @   †>ÐaZ ­pclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt¾ À †"Ð? ;disabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Ð^©default·)" ;disabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ Ð^©default·*" ;disabledpwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm¾  Ð^©default·+" ;disabledpwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm¾ 0Ð^©default·," ;disabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ ` †­i2cÐM©default·-+;okayrtc@51haoyu,hym8563¾Q‰vxin32ki2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c¾   †­i2cÐN©default·.+ ;disabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c¾ à †­i2cÐO©default·/+ ;disabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart¾  †fn6ÐMU­baudclkapb_pclkw|txrx©default ·012-: ;disabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart¾ @ †fn6ÐNV­baudclkapb_pclkw|txrx©default·3-: ;disabledserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart¾ € †fn6ÐOW­baudclkapb_pclkw|txrx©default·4-: ;disabledsaradc@2006c000rockchip,saradc¾ À †Ð[>­saradcapb_pclk×W âsaradc-apbD ;disabledi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c¾   †­i2cÐL©default·5+ ;disabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi¾ @ †ÐAR­spiclkapb_pclkw |txrx©default·6789:+ ;disableddma-controller@20078000arm,pl330arm,primecell¾ €@†VqР­apb_pclkˆethernet@2008c000rockchip,rk3128-gmac¾ À@†89macirqeth_wake_irq8Ð~‚€ÔoM­stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac×8 âstmmacethÁ#“¡ ;disabledmdiosnps,dwmac-mdio+pinctrlrockchip,rk3128-pinctrlÁ#+–gpio@2007c000rockchip,gpio-bank¾ À †$Ð@¯¿þ=gpio@20080000rockchip,gpio-bank¾  †%ÐA¯¿þgpio@20084000rockchip,gpio-bank¾ @ †&ÐB¯¿þ?gpio@20088000rockchip,gpio-bank¾ € †'ÐC¯¿þpcfg-pull-defaultË<�pcfg-pull-noneá;emmcemmc-clkî;emmc-cmdî<�emmc-cmd1î<�emmc-pwrî<�emmc-bus1î<�emmc-bus4@î<�<�<�<�emmc-bus8€î<�<�<�<�<�<�<�<�gmacrgmii-pinsðî<� <� <� <� <�<�<�<�<�<�<�<�<�<�<�rmii-pins î<� <� <�<�<�<�<�<�<�<�hdmihdmii2c-xfer î;;%hdmi-hpdî;&hdmi-cecî;'i2c0i2c0-xfer î;;5i2c1i2c1-xfer î;;-i2c2i2c2-xfer î;;.i2c3i2c3-xfer î;;/i2si2s-bus`î; ; ; ; ;;i2s1-bus`î;;;;;;lcdclcdc-dclkî;lcdc-denî ;lcdc-hsyncî ;lcdc-vsyncî ;lcdc-rgb24àî ; ;;;;;;;;;;;;;nfcflash-aleî;flash-cleî;flash-wrnî;!flash-rdnî;flash-rdyî; flash-cs0î;flash-dqsî;flash-bus8€î;;;;;;;;pwm0pwm0-pinî;)pwm1pwm1-pinî;*pwm2pwm2-pinî;+pwm3pwm3-pinî;,sdiosdio-clkî;sdio-cmdî<�sdio-pwrenî<�sdio-bus4@î<�<�<�<�sdmmcsdmmc-clkî;sdmmc-cmdî<�sdmmc-detî<�sdmmc-wpî<�sdmmc-pwrenî<�sdmmc-bus4@î<�<�<�<�spdifspdif-txî;spi0spi0-clkî<�8spi0-cs0î <�9spi0-txî <�6spi0-rxî <�7spi0-cs1î <�:spi1-clkî<�spi1-cs0î<�spi1-txî<�spi1-rxî<�spi1-cs1î<�spi2-clkî <�spi2-cs0î<�spi2-txî <�spi2-rxî <�uart0uart0-xfer î<�;0uart0-ctsî;1uart0-rtsî;2uart1uart1-xfer î <� <�3uart1-ctsî;uart1-rtsî ;uart2uart2-xfer î<�;4uart2-ctsî;uart2-rtsî;usb-hosthost-vbus-drvî;@usb-otgotg-vbus-drvî;>chosenü/serial@20068000memory@60000000²memory¾`@vcc5v0-otg-regulatorregulator-fixed =©default·>  vcc5v0_otgLK@4LK@vcc5v0-host-regulatorregulator-fixed ?©default·@  vcc5v0_hostLLK@4LK@ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2mmc0interruptsinterrupt-affinityenable-methoddevice_typeregclock-latencyclocksresetsoperating-points-v2#cooling-cellsphandleopp-sharedopp-hzopp-microvoltopp-suspendportsstatusarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domains#power-domain-cellspm_qosreset-namesremote-endpointinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesvbus-supplydmasdma-namesfifo-depthmax-frequencybus-widthpinctrl-namespinctrl-0rockchip,grf#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathgpioregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on