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þílÈ8f´(f|(,chipspark,rayeager-px2rockchip,rk3066a
7Rayeager PX2aliases=/ethernet@10204000G/pinctrl/gpio@20034000M/pinctrl/gpio@2003c000S/pinctrl/gpio@2003e000Y/pinctrl/gpio@20080000_/i2c@2002d000d/i2c@2002f000i/i2c@20056000n/i2c@2005a000s/i2c@2005e000x/serial@10124000€/serial@10126000ˆ/serial@20064000/serial@20068000˜/spi@20070000/spi@20074000¢/pinctrl/gpio@20084000¨/pinctrl/gpio@2000a000®/mmc@10214000³/mmc@10218000¸/mmc@1021c000oscillator,fixed-clock½n6ÍÚxin24míUgpu@10090000",rockchip,rk3066-maliarm,mali-400õ ùÅÅ buscoreÅõá1x 8disabledx?5Jgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3Zvideo-codec@10104000,rockchip,rk3066-vpuõ@?
Jvepuvdpu ùÎØÍ×(aclk_vdpuhclk_vdpuaclk_vepuhclk_vepuZcache-controller@10138000,arm,pl310-cacheõ€hvíHscu@1013c000,arm,cortex-a9-scuõÀglobal-timer@1013c200,arm,cortex-a9-global-timerõ ?ù 8disabledlocal-timer@1013c600,arm,cortex-a9-twd-timerõÆ ?
ùinterrupt-controller@1013d000,arm,cortex-a9-gic‚—õÐÁíserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uartõ@?"¨²baudclkapb_pclkù@L8okay¿ÄtxrxÎdefaultÜserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uartõ`?#¨²baudclkapb_pclkùAM 8disabled¿ÄtxrxÎdefaultÜqos@1012d000,rockchip,rk3066-qossysconõÐ í)qos@1012e000,rockchip,rk3066-qossysconõà í(qos@1012f000,rockchip,rk3066-qossysconõð í"qos@1012f080,rockchip,rk3066-qossysconõð€ í$qos@1012f100,rockchip,rk3066-qossysconõñ í&qos@1012f180,rockchip,rk3066-qossysconõñ€ í#qos@1012f200,rockchip,rk3066-qossysconõò í%qos@1012f280,rockchip,rk3066-qossysconõò€ í'usb@10180000,rockchip,rk3066-usbsnps,dwc2õ?ùÃotgæotg@@ #usb2-phy8okayusb@101c0000
,snps,dwc2õ?ùÉotgæhost
#usb2-phy8okayÎdefaultÜethernet@10204000,rockchip,rk3066-emacõ @<�?-
ùÄDhclkmacref:dDrmii8okayMQÎdefaultÜmdioethernet-phy@0õ\ímmc@10214000,rockchip,rk2928-dw-mshcõ!@?ùÀHbiuciu¿Ärx-txh1Qsreset8okay½úð€úð€ÎdefaultÜ—¢®Àmmc@10218000,rockchip,rk2928-dw-mshcõ!€?ùÁIbiuciu¿Ärx-txh1Rsreset8okayÎdefaultÜÑ¢mmc@1021c000,rockchip,rk2928-dw-mshcõ!À?ùÂJbiuciu¿Ärx-txh1Ssreset8okay®ÑÎdefaultÜ ¢!ß!nand-controller@10500000,rockchip,rk2928-nfcõP@?ùÓahb 8disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfdõ @reboot-mode,syscon-reboot-modeì@óRBÃÿRBÃ
RBà RBÃpower-controller!,rockchip,rk3066-power-controller)ípower-domain@7õˆùÃľ¿ÍÎPÇÖOÊÐÙÈÑÉÒ="#$%&')power-domain@6õ ùÎÍØ×=()power-domain@8õùÅ=))grf@20008000&,rockchip,rk3066-grfsysconsimple-mfdõ €í
usbphy,rockchip,rk3066a-usb-phy8okayusb-phy@17cõ|ùQphyclkÍDí usb-phy@188õˆùRphyclkÍDí
dma-controller@20018000,arm,pl330arm,primecellõ €@?OZuùÀ apb_pclkídma-controller@2001c000,arm,pl330arm,primecellõ À@?OZuùÀ apb_pclk 8disabledi2c@2002d000,rockchip,rk3066-i2cõ Ð?(-
i2cùP8okayÎdefaultÜ*½€ak8963@d,asahi-kasei,ak8975õ
+?ÎdefaultÜ,mma8452@1d,fsl,mma8452õ+?ÎdefaultÜ-i2c@2002f000,rockchip,rk3066-i2cõ ð?)-
ùQi2c8okayÎdefaultÜ.½€tps@2dõ-/?ÎdefaultÜ01Œ2˜2¤2°2¼3È3Ô2à2,ti,tps65910regulatorsregulator@0ívcc_rtcüõvrtcregulator@1ívcc_io%2Z =2Z üõvioí3regulator@2ívdd_arm% 'À=ã`üUõvdd1íIregulator@3ívcc_ddr% 'À=ã`üUõvdd2regulator@5ívcc18%w@=w@üõvdig1regulator@6ívdd_11%Èà=Èàüõvdig2regulator@7ívcc_25%&% =&% üõvpllí?regulator@8 ívccio_wl%w@=w@õvdacíregulator@9ívcc25_hdmi%&% =&% õ vaux1regulator@10ívcca_33%2Z =2Z õ
vaux2regulator@11 ívcc_rmii%2Z =2Z õvaux33íregulator@12
ívcc28_cif%*¹€=*¹€õvmmcregulator@4õvdd3regulator@13õ
vbbpwm@20030000,rockchip,rk2928-pwmõ gùF 8disabledÎdefaultÜ4pwm@20030010,rockchip,rk2928-pwmõ gùF8okayÎdefaultÜ5watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdtõ ÀùK?38okaypwm@20050020,rockchip,rk2928-pwmõ gùG8okayÎdefaultÜ6pwm@20050030,rockchip,rk2928-pwmõ 0gùG8okayÎdefaultÜ7í[i2c@20056000,rockchip,rk3066-i2cõ `?*-
ùRi2c8okayÎdefaultÜ8i2c@2005a000,rockchip,rk3066-i2cõ ?+-
ùSi2c8okayÎdefaultÜ9i2c@2005e000,rockchip,rk3066-i2cõ à?4-
ùTi2c8okayÎdefaultÜ:serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uartõ @?$¨²baudclkapb_pclkùBN8okay¿ÄtxrxÎdefaultÜ;serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uartõ €?%¨²baudclkapb_pclkùCO8okay¿ ÄtxrxÎdefaultÜ<�=>saradc@2006c000,rockchip,saradcõ À?rùGJsaradcapb_pclk1Wssaradc-apb8okay„?spi@20070000,rockchip,rk3066-spiùEHspiclkapb_pclk?&õ ¿
Ätxrx8okayÎdefaultÜ@ABCspi@20074000,rockchip,rk3066-spiùFIspiclkapb_pclk?'õ @¿
Ätxrx 8disabledÎdefaultÜDEFGdma-controller@20078000,arm,pl330arm,primecellõ €@?OZuùÁ apb_pclkícpusrockchip,rk3066-smpcpu@0žcpu,arm,cortex-a9ªHõ8»›@Ö O€íØa€*ˆs€*ˆ 'ÀÈà°ÀÈàÂÀg8Ìœ@ùÚIcpu@1žcpu,arm,cortex-a9ªHõÚIdisplay-subsystem,rockchip,display-subsystemåJKsram@10080000
,mmio-sramõësmp-sram@0,rockchip,rk3066-smp-sramõPvop@1010c000,rockchip,rk3066-vopõÀœ?
ùþÍaclk_vopdclk_vophclk_vopZ1def
saxiahbdclk 8disabledportíJendpoint@0õòLíPvop@1010e000,rockchip,rk3066-vopõàœ?ùÄ¿Îaclk_vopdclk_vophclk_vopZ1ghi
saxiahbdclk 8disabledportíKendpoint@0õòMíQhdmi@10116000,rockchip,rk3066-hdmiõ` ?@ùÙhclkÎdefaultÜNOZ-
8disabledportsport@0õendpoint@0õòPíLendpoint@1õòQíMport@1õi2s@10118000,rockchip,rk3066-i2sõ€ ?ÎdefaultÜRùKÆi2s_clki2s_hclk¿Ätxrx. 8disabledi2s@1011a000,rockchip,rk3066-i2sõ ? ÎdefaultÜSùLÇi2s_clki2s_hclk¿Ätxrx. 8disabledi2s@1011c000,rockchip,rk3066-i2sõÀ ?ÎdefaultÜTùMÈi2s_clki2s_hclk¿
Ätxrx. 8disabledclock-controller@20000000,rockchip,rk3066a-cruõ ùUxin24m-
ÍH@ËÔ^ÌÕ_ ׄ#g¸€á£ðÑ€xhÀá£ðÑ€xhÀítimer@2000e000,snps,dw-apb-timerõ à?.ùVDtimerpclkefuse@20010000,rockchip,rk3066a-efuseõ @ù[pclk_efusecpu_leakage@17õtimer@20038000,snps,dw-apb-timerõ €?,ùTBtimerpclktimer@2003a000,snps,dw-apb-timerõ ?-ùUCtimerpclktsadc@20060000,rockchip,rk3066-tsadcõ ù]]saradcapb_pclk?r1\ssaradc-apb 8disabledpinctrl,rockchip,rk3066a-pinctrl-
ëgpio@20034000,rockchip,gpio-bankõ @?6ùUUe‚—í`gpio@2003c000,rockchip,gpio-bankõ À?7ùVUe‚—ígpio@2003e000,rockchip,gpio-bankõ à?8ùWUe‚—gpio@20080000,rockchip,gpio-bankõ ?9ùXUe‚—í^gpio@20084000,rockchip,gpio-bankõ @?:ùYUe‚—í+gpio@2000a000,rockchip,gpio-bankõ ?<�ùZUe‚—í/pcfg-pull-defaultqíXpcfg-pull-none‡íVemacemac-xfer€”VVVVVVVVíemac-mdio ”VVírmii-rst”Wíemmcemmc-clk”Xíemmc-cmd” Xíemmc-rst”
Xí hdmihdmi-hpd”XíOhdmii2c-xfer ”VVíNi2c0i2c0-xfer ”VVí*i2c1i2c1-xfer ”VVí.i2c2i2c2-xfer ”VVí8i2c3i2c3-xfer ”VVí9i2c4i2c4-xfer ”VVí:pwm0pwm0-out”Ví4pwm1pwm1-out”Ví5pwm2pwm2-out”Ví6pwm3pwm3-out”Ví7spi0spi0-clk”Xí@spi0-cs0”XíCspi0-tx”XíAspi0-rx”XíBspi0-cs1”Xspi1spi1-clk”XíDspi1-cs0”XíGspi1-rx”XíFspi1-tx”XíEspi1-cs1”Xuart0uart0-xfer ”XXíuart0-cts”Xíuart0-rts”Xíuart1uart1-xfer ”XXíuart1-cts”Xuart1-rts”Xuart2uart2-xfer ”X Xí;uart3uart3-xfer ”XXí<�uart3-cts”Xí=uart3-rts”Xí>sd0sd0-clk”Xísd0-cmd” Xísd0-cd”Xísd0-wp”Xsd0-bus-width1”
Xsd0-bus-width4@”
XXX
Xísd1sd1-clk”Xísd1-cmd”Xísd1-cd”Xsd1-wp”Xsd1-bus-width1”Xsd1-bus-width4@”XXXXíi2s0i2s0-bus”XX X
XXX
XXXíRi2s1i2s1-bus`”XXXXXXíSi2s2i2s2-bus`”XXXXXXíTpcfg-output-high¢íWak8963comp-int”Xí,irir-int”XíYkeyspwr-key”XíZmma8452gsensor-int”Xí-mmcsdmmc-pwr”Xí_usb_hosthost-drv”Xíahub-rst”Wísata-pwr”Xí\sata-reset”
Wíusb_otgotg-drv”Xíbtpspmic-int”Xí0pwr-hold”Wí1memory@60000000žmemoryõ`@ir-receiver,gpio-ir-receiverb/ÎdefaultÜYgpio-keys
,gpio-keyskey-power®b/¼GPIO PowerÂtÎdefaultÜZvdd-log,pwm-regulatorÍ[èívdd_log%O€=O€üÒB@dO€*8okayvsys-regulator,regulator-fixedívsys%LK@=LK@üUí2stdby-regulator,regulator-fixed í5v_stdby%LK@=LK@üUí]emmc-regulator,regulator-fixed
íemmc_vccq%-ÆÀ=-ÆÀà2í!sata-regulator,regulator-fixedëþ+ÎdefaultÜ\íusb_5v%LK@=LK@üà]sdmmc-regulator,regulator-fixedþ^ÎdefaultÜ_ívcc_sd%2Z =2Z † à3íusb-host-regulator,regulator-fixedëþ`ÎdefaultÜa íhost-pwr%LK@=LK@üà]usb-otg-regulator,regulator-fixedëþ`ÎdefaultÜbívcc_otg%LK@=LK@üà] #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0gpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1gpio4gpio6mmc0mmc1mmc2clock-frequency#clock-cellsclock-output-namesphandleregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyreset-gpiosfifo-depthreset-namesmax-frequencybus-widthdisable-wpvmmc-supplycap-mmc-highspeedcap-sd-highspeednon-removablevqmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsvref-supplyenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsrangesremote-endpoint#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highwakeup-sourcelabellinux,codepwmsvoltage-tablevin-supplyenable-active-highgpiostartup-delay-us