Ð þí>Ì8:ˆ(D:P$rockchip,rk3036-evbrockchip,rk3036&!7Rockchip RK3036 Evaluation boardaliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/i2c@20072000T/i2c@20056000Y/i2c@2005a000^/mmc@1021c000d/mmc@10214000j/mmc@10218000p/serial@20060000x/serial@20064000€/serial@20068000ˆ/spi@20074000cpusŒrockchip,rk3036-smpcpu@f00šcpuarm,cortex-a7¦ª± s€B@Âœ@Ð×cpu@f01šcpuarm,cortex-a7¦ª×arm-pmuarm,cortex-a7-pmußLMêdisplay-subsystemrockchip,display-subsystemýtimerarm,armv7-timer0ß   'n6oscillator fixed-clock'n67xin24mJ×sram@10080000 mmio-sram¦  W smp-sram@0rockchip,rk3066-smp-sram¦gpu@10090000"rockchip,rk3036-maliarm,mali-400¦ 0ß^gpgpmmupp0ppmmu0n@~õáÐ@@ “buscoreŸªx ­disabledvideo-codec@10108000rockchip,rk3036-vpu¦€ ß^vdpuÐÐÜ “aclkhclk´Ÿiommu@10108800rockchip,iommu¦ˆ ß7ÐÐÜ “aclkifaceŸ»×vop@10118000rockchip,rk3036-vop¦€œ ß+ÐÅdÑ“aclk_vopdclk_vophclk_vopªuvw Èaxiahbdclk´Ÿ ­disabledport×endpoint@0¦Ô × iommu@10118300rockchip,iommu¦ƒ ß+ÐÅÑ “aclkifaceŸ» ­disabled×qos@1012d000rockchip,rk3036-qossyscon¦Ð ×qos@1012e000rockchip,rk3036-qossyscon¦à ×qos@1012f000rockchip,rk3036-qossyscon¦ð ×interrupt-controller@10139000 arm,gic-400äù ¦  À à  ß ×usb@101800002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2¦ ß ÐÁ“otg otg$3€€@@  ­disabledusb@101c00002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2¦ ß Ð“otg host ­disabledethernet@10200000rockchip,rk3036-emac¦ @ ßB Ð̘—“hclkmacrefmacclkn™Ofdprmii­okayy }    default® mdioethernet-phy@0¦× mmc@102140000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc¦!@@'<4`¸<4`ÐÈD“biuciuÆ ßªQÈreset ­disabledmmc@102180000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc¦!€@¸<4` ÐÉEsw“biuciuciu-driveciu-sampleÆ ßªRÈreset ­disabledmmc@1021c0000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc¦!À@ ßÑÛ'<4`¸<4` ÐËGuy“biuciuciu-driveciu-sampleíø ýrx-txÆ default ®ªSÈreset ­disabledi2s@10220000(rockchip,rk3036-i2srockchip,rk3066-i2s¦"@ ß3“i2s_clki2s_hclkÐRÎøýtxrx default®" ­disablednand-controller@10500000(rockchip,rk3036-nfcrockchip,rk2928-nfc¦P@ ßÐÅL“ahbnfcnL~ðÑ€® default ­disabledclock-controller@20000000rockchip,rk3036-cru¦ Гxin24mB J3n~#g¸€×syscon@20008000&rockchip,rk3036-grfsysconsimple-mfd¦ €× power-controller!rockchip,rk3036-power-controller@×power-domain@3¦ÐÅÑdT@power-domain@4¦ÐÐÜT@power-domain@5¦Ð@T@reboot-modesyscon-reboot-mode[ØbRBÃnRBÃ|RBà ŒRBÃacodec-ana@20030000 rk3036-codec¦ @B  “acodec_pclkÐq ­disabledhdmi@20034000rockchip,rk3036-inno-hdmi¦ @@ ß-Ðh“pclkB  default® ­disabledportsport@0¦endpointÔ × port@1¦timer@20044000,rockchip,rk3036-timerrockchip,rk3288-timer¦ @  ß Ða “pclktimerpwm@20050000(rockchip,rk3036-pwmrockchip,rk2928-pwm¦ ˜Ð^ default®! ­disabledpwm@20050010(rockchip,rk3036-pwmrockchip,rk2928-pwm¦ ˜Ð^ default®" ­disabledpwm@20050020(rockchip,rk3036-pwmrockchip,rk2928-pwm¦  ˜Ð^ default®# ­disabledpwm@20050030(rockchip,rk3036-pwmrockchip,rk2928-pwm¦ 0˜Ð^ default®$ ­disabledi2c@20056000(rockchip,rk3036-i2crockchip,rk3288-i2c¦ ` ß“i2cÐM default®%­okayrtc@51haoyu,hym8563¦QJ7xin32ki2c@2005a000(rockchip,rk3036-i2crockchip,rk3288-i2c¦   ß“i2cÐN default®& ­disabledserial@20060000&rockchip,rk3036-uartsnps,dw-apb-uart¦  ߣ­'n6ÐMU“baudclkapb_pclk default ®'() ­disabledserial@20064000&rockchip,rk3036-uartsnps,dw-apb-uart¦ @ ߣ­'n6ÐNV“baudclkapb_pclk default®* ­disabledserial@20068000&rockchip,rk3036-uartsnps,dw-apb-uart¦ € ߣ­'n6ÐOW“baudclkapb_pclk default®+­okayi2c@20072000(rockchip,rk3036-i2crockchip,rk3288-i2c¦   ß“i2cÐL default®, ­disabledspi@20074000rockchip,rockchip-spi¦ @ ßÐRA“apb-pclkspi_pclkø ýtxrx default®-./0 ­disableddma-controller@20078000arm,pl330arm,primecell¦ €@ߺÅàР“apb_pclk×pinctrlrockchip,rk3036-pinctrlB Wgpio@2007c000rockchip,gpio-bank¦ À ß$Ð@÷äùgpio@20080000rockchip,gpio-bank¦  ß%ÐA÷äùgpio@20084000rockchip,gpio-bank¦ @ ß&ÐB÷äù× pcfg-pull-default×2pcfg-pull-none)×1pwm0pwm0-pin61×!pwm1pwm1-pin61×"pwm2pwm2-pin61×#pwm3pwm3-pin61×$sdmmcsdmmc-clk61sdmmc-cmd62sdmmc-cd62sdmmc-bus162sdmmc-bus4@62222sdiosdio-bus16 2sdio-bus4@6 2 2 22sdio-cmd62sdio-clk6 1emmcemmc-clk61×emmc-cmd62×emmc-bus8€622222222×nfcflash-ale62×flash-bus8€622222222×flash-cle62×flash-csn062×flash-rdn62×flash-rdy62×flash-wrn62×emacemac-xfer€6 2 2222222× emac-mdio 6 22×i2c0i2c0-xfer 611×,i2c1i2c1-xfer 611×%i2c2i2c2-xfer 611×&i2si2s-bus`6222222×hdmihdmi-ctl@61 1 1 1×uart0uart0-xfer 621×'uart0-cts62×(uart0-rts61×)uart1uart1-xfer 621×*uart2uart2-xfer 621×+spi-pinsspi-txd62×-spi-rxd62×.spi-clk62×/spi-cs062×0spi-cs162memory@60000000šmemory¦`@ #address-cells#size-cellscompatibleinterrupt-parentmodelgpio0gpio1gpio2i2c0i2c1i2c2mshc0mshc1mshc2serial0serial1serial2spienable-methoddevice_typeregresetsoperating-pointsclock-latencyclocksphandleinterruptsinterrupt-affinityportsarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesassigned-clocksassigned-clock-ratesclock-namespower-domainsstatusiommus#iommu-cellsreset-namesremote-endpointinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,grfassigned-clock-parentsmax-speedphy-modephyphy-reset-durationphy-reset-gpiospinctrl-namespinctrl-0max-frequencyfifo-depthbus-widthcap-mmc-highspeeddisable-wpdmasdma-namesmmc-ddr-1_8vnon-removable#sound-dai-cells#reset-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#pwm-cellsreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pins