Ð þí¸8X( ` -compulab,omap3-cm-t3730ti,omap3630ti,omap3 +7CompuLab CM-T3730chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8{cpu‡‹’cpuž“à¬ÀËÚæpmu@54000000arm,cortex-a8-pmu‡T€îùdebugsssocti,omap-inframpu ti,omap3-mpuùmpuiva ti,iva2.2ùivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus‡hî +ùl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus‡ +  pinmux@30 ti,omap3-padconfpinctrl-single‡08+ *?]ÿuart3-pinsznpæçmmc1-pins0zæôgreen-led-pinsz²ædss-dpi-common-pins°z¤¦¨ª¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚæ dss-dpi-cm-t35x-pins0z¬®°²´¶ads7846-pinszŠæðmcspi1-pins z˜šœžæïi2c1-pinszŠŒæèmcbsp2-pins z æýsmsc1-pinszˆjæ hsusb0-pins`zrtvxz|~€‚„†ˆæ twl4030-pinsz°Aæémmc2-pins0z(*,.02æöwl12xx-gpio-pinsz²4æ scm_conf@270sysconsimple-bus‡p0+ p0æpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap‡°Žpbias_mmc_omap2430•pbias_mmc_omap2430¤w@¼-ÆÀæóclocks+clock@68 ti,clksel‡hÔ+clock-mcbsp5-mux-fck@4‡Ôti,composite-mux-clockámcbsp5_mux_fck‹æ clock-mcbsp3-mux-fck@0‡Ôti,composite-mux-clockámcbsp3_mux_fck‹ æclock-mcbsp4-mux-fck@2‡Ôti,composite-mux-clockámcbsp4_mux_fck‹ æmcbsp5_fckÔti,composite-clock‹ æclock@4 ti,clksel‡Ô+clock-mcbsp1-mux-fck@2‡Ôti,composite-mux-clockámcbsp1_mux_fck‹æ clock-mcbsp2-mux-fck@6‡Ôti,composite-mux-clockámcbsp2_mux_fck‹ æmcbsp1_fckÔti,composite-clock‹ æúmcbsp2_fckÔti,composite-clock‹æümcbsp3_fckÔti,composite-clock‹æþmcbsp4_fckÔti,composite-clock‹æÿclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single‡ \+ *?]ÿtwl4030-vpins-pins zæêdss-dpi-cm-t3730-pins0z ætarget-module@480a6000ti,sysc-omap2ti,sysc‡H `DH `HH `Lôrevsyscsyssþ  ‹’ick+ H ` aes1@0 ti,omap3-aes‡Pî&  +txrxtarget-module@480c5000ti,sysc-omap2ti,sysc‡H PDH PHH PLôrevsyscsyssþ  ‹’ick+ H P aes2@0 ti,omap3-aes‡Pî&AB+txrxprm@48306000 ti,omap3-prm‡H0`@î clocks+virt_16_8m_ckÔ fixed-clock5Yæosc_sys_ck@d40Ô ti,mux-clock‹‡ @æsys_ck@1270Ôti,divider-clock‹ER‡p]æ"sys_clkout1@d70Ôti,gate-clock‹‡ pEdpll3_x2_ckÔfixed-factor-clock‹tdpll3_m2x2_ckÔfixed-factor-clock‹tæ!dpll4_x2_ckÔfixed-factor-clock‹ tcorex2_fckÔfixed-factor-clock‹!tæ#wkup_l4_ickÔfixed-factor-clock‹"tæbcorex2_d3_fckÔfixed-factor-clock‹#tæŠcorex2_d5_fckÔfixed-factor-clock‹#tæ‹clockdomainscm@48004000 ti,omap3-cm‡H@@clocks+dummy_apb_pclkÔ fixed-clock5omap_32k_fckÔ fixed-clock5€æHvirt_12m_ckÔ fixed-clock5·ævirt_13m_ckÔ fixed-clock5Æ]@ævirt_19200000_ckÔ fixed-clock5$øævirt_26000000_ckÔ fixed-clock5Œº€ævirt_38_4m_ckÔ fixed-clock5Iðædpll4_ck@d00Ôti,omap3-dpll-per-j-type-clock‹""‡ D 0æ dpll4_m2_ck@d48Ôti,divider-clock‹ R?‡ H]æ$dpll4_m2x2_mul_ckÔfixed-factor-clock‹$tæ%dpll4_m2x2_ck@d00Ôti,hsdiv-gate-clock‹%E‡ ‰æ&omap_96m_alwon_fckÔfixed-factor-clock‹&tæ2dpll3_ck@d00Ôti,omap3-dpll-core-clock‹""‡ @ 0æclock@1140 ti,clksel‡@Ô+clock-dpll3-m3@16‡Ôti,divider-clock ádpll3_m3_ck‹R]æ,clock-dpll4-m6@24‡Ôti,divider-clock ádpll4_m6_ck‹ R?]æ>clock-emu-src-mux@0‡Ô ti,mux-clockáemu_src_mux_ck‹"'()ævclock-pclk-fck@8‡Ôti,divider-clock ápclk_fck‹*R]clock-pclkx2-fck@6‡Ôti,divider-clock ápclkx2_fck‹*R]clock-atclk-fck@4‡Ôti,divider-clock áatclk_fck‹*R]clock-traceclk-src-fck@2‡Ô ti,mux-clockátraceclk_src_fck‹"'()æ+clock-traceclk-fck@11‡ Ôti,divider-clock átraceclk_fck‹+R]dpll3_m3x2_mul_ckÔfixed-factor-clock‹,tæ-dpll3_m3x2_ck@d00Ôti,hsdiv-gate-clock‹-E ‡ ‰æ.emu_core_alwon_ckÔfixed-factor-clock‹.tæ'sys_altclkÔ fixed-clock5æ5mcbsp_clksÔ fixed-clock5æcore_ckÔfixed-factor-clock‹tæ/dpll1_fck@940Ôti,divider-clock‹/ER‡ @]æ0dpll1_ck@904Ôti,omap3-dpll-clock‹"0‡  $ @ 4ædpll1_x2_ckÔfixed-factor-clock‹tæ1dpll1_x2m2_ck@944Ôti,divider-clock‹1R‡ D]æEcm_96m_fckÔfixed-factor-clock‹2tæ3clock@d40 ti,clksel‡ @Ô+clock-dpll3-m2@27‡Ôti,divider-clock ádpll3_m2_ck‹R]æclock-omap-96m-fck@6‡Ô ti,mux-clock áomap_96m_fck‹3"æYclock-omap-54m-fck@5‡Ô ti,mux-clock áomap_54m_fck‹45æAclock-omap-48m-fck@3‡Ô ti,mux-clock áomap_48m_fck‹65æ9clock@e40 ti,clksel‡@Ô+clock-dpll4-m3@8‡Ôti,divider-clock ádpll4_m3_ck‹ R ]æ7clock-dpll4-m4@0‡Ôti,divider-clock ádpll4_m4_ck‹ R]æ:dpll4_m3x2_mul_ckÔfixed-factor-clock‹7tæ8dpll4_m3x2_ck@d00Ôti,hsdiv-gate-clock‹8E‡ ‰æ4cm_96m_d2_fckÔfixed-factor-clock‹3tæ6omap_12m_fckÔfixed-factor-clock‹9tæZdpll4_m4x2_mul_ckÔti,fixed-factor-clock‹:Ÿ­ºæ;dpll4_m4x2_ck@d00Ôti,gate-clock‹;E‡ ‰ºæ^dpll4_m5_ck@f40Ôti,divider-clock‹ R?‡@]æ<�dpll4_m5x2_mul_ckÔti,fixed-factor-clock‹<�Ÿ­ºæ=dpll4_m5x2_ck@d00Ôti,hsdiv-gate-clock‹=E‡ ‰ºæzdpll4_m6x2_mul_ckÔfixed-factor-clock‹>tæ?dpll4_m6x2_ck@d00Ôti,hsdiv-gate-clock‹?E‡ ‰æ@emu_per_alwon_ckÔfixed-factor-clock‹@tæ(clock@d70 ti,clksel‡ pÔ+clock-clkout2-src-gate@7‡Ô ti,composite-no-wait-gate-clockáclkout2_src_gate_ck‹/æCclock-clkout2-src-mux@0‡Ôti,composite-mux-clockáclkout2_src_mux_ck‹/"3AæDclock-sys-clkout2@3‡Ôti,divider-clock ásys_clkout2‹BR@Íclkout2_src_ckÔti,composite-clock‹CDæBmpu_ckÔfixed-factor-clock‹EtæFarm_fck@924Ôti,divider-clock‹F‡ $Remu_mpu_alwon_ckÔfixed-factor-clock‹Ftæ)clock@a40 ti,clksel‡ @Ô+clock-l3-ick@0‡Ôti,divider-clockál3_ick‹/R]æGclock-l4-ick@2‡Ôti,divider-clockál4_ick‹GR]æIclock-gpt10-mux-fck@6‡Ôti,composite-mux-clockágpt10_mux_fck‹H"æVclock-gpt11-mux-fck@7‡Ôti,composite-mux-clockágpt11_mux_fck‹H"æXclock-ssi-ssr-div-fck-3430es2@8‡Ôti,composite-divider-clockássi_ssr_div_fck_3430es2‹#$ãæclock@c40 ti,clksel‡ @Ô+clock-rm-ick@1‡Ôti,divider-clockárm_ick‹IR]clock-gpt1-mux-fck@0‡Ôti,composite-mux-clock ágpt1_mux_fck‹H"æaclock-usim-mux-fck@3‡Ôti,composite-mux-clock áusim_mux_fck(‹"JKLMNOPQR]æƒclock@a00 ti,clksel‡ Ô+clock-gpt10-gate-fck@11‡ Ôti,composite-gate-clockágpt10_gate_fck‹"æUclock-gpt11-gate-fck@12‡ Ôti,composite-gate-clockágpt11_gate_fck‹"æWclock-mmchs2-fck@25‡Ôti,wait-gate-clock ámmchs2_fck‹æ¹clock-mmchs1-fck@24‡Ôti,wait-gate-clock ámmchs1_fck‹æºclock-i2c3-fck@17‡Ôti,wait-gate-clock ái2c3_fck‹æ»clock-i2c2-fck@16‡Ôti,wait-gate-clock ái2c2_fck‹æ¼clock-i2c1-fck@15‡Ôti,wait-gate-clock ái2c1_fck‹æ½clock-mcbsp5-gate-fck@10‡ Ôti,composite-gate-clockámcbsp5_gate_fck‹æ clock-mcbsp1-gate-fck@9‡ Ôti,composite-gate-clockámcbsp1_gate_fck‹æ clock-mcspi4-fck@21‡Ôti,wait-gate-clock ámcspi4_fck‹Sæ¾clock-mcspi3-fck@20‡Ôti,wait-gate-clock ámcspi3_fck‹Sæ¿clock-mcspi2-fck@19‡Ôti,wait-gate-clock ámcspi2_fck‹SæÀclock-mcspi1-fck@18‡Ôti,wait-gate-clock ámcspi1_fck‹SæÁclock-uart2-fck@14‡Ôti,wait-gate-clock áuart2_fck‹SæÂclock-uart1-fck@13‡ Ôti,wait-gate-clock áuart1_fck‹SæÃclock-hdq-fck@22‡Ôti,wait-gate-clockáhdq_fck‹TæÄclock-modem-fck@31‡Ôti,omap3-interface-clock ámodem_fck‹"æàclock-mspro-fck@23‡Ôti,wait-gate-clock ámspro_fck‹clock-ssi-ssr-gate-fck-3430es2@0‡Ô ti,composite-no-wait-gate-clockássi_ssr_gate_fck_3430es2‹#æ~clock-mmchs3-fck@30‡Ôti,wait-gate-clock ámmchs3_fck‹æÜgpt10_fckÔti,composite-clock‹UVgpt11_fckÔti,composite-clock‹WXcore_96m_fckÔfixed-factor-clock‹Ytæcore_48m_fckÔfixed-factor-clock‹9tæScore_12m_fckÔfixed-factor-clock‹ZtæTcore_l3_ickÔfixed-factor-clock‹Gtæ[clock@a10 ti,clksel‡ Ô+clock-sdrc-ick@1‡Ôti,wait-gate-clock ásdrc_ick‹[æŽclock-mmchs2-ick@25‡Ôti,omap3-interface-clock ámmchs2_ick‹\æÅclock-mmchs1-ick@24‡Ôti,omap3-interface-clock ámmchs1_ick‹\æÆclock-hdq-ick@22‡Ôti,omap3-interface-clockáhdq_ick‹\æÇclock-mcspi4-ick@21‡Ôti,omap3-interface-clock ámcspi4_ick‹\æÈclock-mcspi3-ick@20‡Ôti,omap3-interface-clock ámcspi3_ick‹\æÉclock-mcspi2-ick@19‡Ôti,omap3-interface-clock ámcspi2_ick‹\æÊclock-mcspi1-ick@18‡Ôti,omap3-interface-clock ámcspi1_ick‹\æËclock-i2c3-ick@17‡Ôti,omap3-interface-clock ái2c3_ick‹\æÌclock-i2c2-ick@16‡Ôti,omap3-interface-clock ái2c2_ick‹\æÍclock-i2c1-ick@15‡Ôti,omap3-interface-clock ái2c1_ick‹\æÎclock-uart2-ick@14‡Ôti,omap3-interface-clock áuart2_ick‹\æÏclock-uart1-ick@13‡ Ôti,omap3-interface-clock áuart1_ick‹\æÐclock-gpt11-ick@12‡ Ôti,omap3-interface-clock ágpt11_ick‹\æÑclock-gpt10-ick@11‡ Ôti,omap3-interface-clock ágpt10_ick‹\æÒclock-mcbsp5-ick@10‡ Ôti,omap3-interface-clock ámcbsp5_ick‹\æÓclock-mcbsp1-ick@9‡ Ôti,omap3-interface-clock ámcbsp1_ick‹\æÔclock-omapctrl-ick@6‡Ôti,omap3-interface-clock áomapctrl_ick‹\æÕclock-aes2-ick@28‡Ôti,omap3-interface-clock áaes2_ick‹\æclock-sha12-ick@27‡Ôti,omap3-interface-clock ásha12_ick‹\æÖclock-icr-ick@29‡Ôti,omap3-interface-clockáicr_ick‹\clock-des2-ick@26‡Ôti,omap3-interface-clock ádes2_ick‹\clock-mspro-ick@23‡Ôti,omap3-interface-clock ámspro_ick‹\clock-mailboxes-ick@7‡Ôti,omap3-interface-clockámailboxes_ick‹\clock-sad2d-ick@3‡Ôti,omap3-interface-clock ásad2d_ick‹Gæáclock-hsotgusb-ick-3430es2@4‡Ô"ti,omap3-hsotgusb-interface-clockáhsotgusb_ick_3430es2‹[æclock-ssi-ick-3430es2@0‡Ôti,omap3-ssi-interface-clockássi_ick_3430es2‹]æclock-mmchs3-ick@30‡Ôti,omap3-interface-clock ámmchs3_ick‹\æÛgpmc_fckÔfixed-factor-clock‹[tcore_l4_ickÔfixed-factor-clock‹Itæ\clock@e00 ti,clksel‡Ô+clock-dss-tv-fckÔti,gate-clock ádss_tv_fck‹AEæ´clock-dss-96m-fckÔti,gate-clock ádss_96m_fck‹YEæµclock-dss2-alwon-fckÔti,gate-clockádss2_alwon_fck‹"Eæ¶clock-dss1-alwon-fck-3430es2@0‡Ôti,dss-gate-clockádss1_alwon_fck_3430es2‹^ºæ·dummy_ckÔ fixed-clock5clock@c00 ti,clksel‡ Ô+clock-gpt1-gate-fck@0‡Ôti,composite-gate-clockágpt1_gate_fck‹"æ`clock-gpio1-dbck@3‡Ôti,gate-clock ágpio1_dbck‹_æ«clock-wdt2-fck@5‡Ôti,wait-gate-clock áwdt2_fck‹_æ¬clock-sr1-fck@6‡Ôti,wait-gate-clockásr1_fck‹"æclock-sr2-fck@7‡Ôti,wait-gate-clockásr2_fck‹"æclock-usim-gate-fck@9‡ Ôti,composite-gate-clockáusim_gate_fck‹Yæ‚gpt1_fckÔti,composite-clock‹`aæwkup_32k_fckÔfixed-factor-clock‹Htæ_clock@c10 ti,clksel‡ Ô+clock-wdt2-ick@5‡Ôti,omap3-interface-clock áwdt2_ick‹bæ­clock-wdt1-ick@4‡Ôti,omap3-interface-clock áwdt1_ick‹bæ®clock-gpio1-ick@3‡Ôti,omap3-interface-clock ágpio1_ick‹bæ¯clock-omap-32ksync-ick@2‡Ôti,omap3-interface-clockáomap_32ksync_ick‹bæ°clock-gpt12-ick@1‡Ôti,omap3-interface-clock ágpt12_ick‹bæ±clock-gpt1-ick@0‡Ôti,omap3-interface-clock ágpt1_ick‹bæ²clock-usim-ick@9‡ Ôti,omap3-interface-clock áusim_ick‹bæ³per_96m_fckÔfixed-factor-clock‹2tæ per_48m_fckÔfixed-factor-clock‹9tæcclock@1000 ti,clksel‡Ô+clock-uart3-fck@11‡ Ôti,wait-gate-clock áuart3_fck‹cæclock-gpt2-gate-fck@3‡Ôti,composite-gate-clockágpt2_gate_fck‹"æeclock-gpt3-gate-fck@4‡Ôti,composite-gate-clockágpt3_gate_fck‹"ægclock-gpt4-gate-fck@5‡Ôti,composite-gate-clockágpt4_gate_fck‹"æiclock-gpt5-gate-fck@6‡Ôti,composite-gate-clockágpt5_gate_fck‹"ækclock-gpt6-gate-fck@7‡Ôti,composite-gate-clockágpt6_gate_fck‹"æmclock-gpt7-gate-fck@8‡Ôti,composite-gate-clockágpt7_gate_fck‹"æoclock-gpt8-gate-fck@9‡ Ôti,composite-gate-clockágpt8_gate_fck‹"æqclock-gpt9-gate-fck@10‡ Ôti,composite-gate-clockágpt9_gate_fck‹"æsclock-gpio6-dbck@17‡Ôti,gate-clock ágpio6_dbck‹dæ‘clock-gpio5-dbck@16‡Ôti,gate-clock ágpio5_dbck‹dæ’clock-gpio4-dbck@15‡Ôti,gate-clock ágpio4_dbck‹dæ“clock-gpio3-dbck@14‡Ôti,gate-clock ágpio3_dbck‹dæ”clock-gpio2-dbck@13‡ Ôti,gate-clock ágpio2_dbck‹dæ•clock-wdt3-fck@12‡ Ôti,wait-gate-clock áwdt3_fck‹dæ–clock-mcbsp2-gate-fck@0‡Ôti,composite-gate-clockámcbsp2_gate_fck‹æclock-mcbsp3-gate-fck@1‡Ôti,composite-gate-clockámcbsp3_gate_fck‹æclock-mcbsp4-gate-fck@2‡Ôti,composite-gate-clockámcbsp4_gate_fck‹æclock-uart4-fck@18‡Ôti,wait-gate-clock áuart4_fck‹cæªclock@1040 ti,clksel‡@Ô+clock-gpt2-mux-fck@0‡Ôti,composite-mux-clock ágpt2_mux_fck‹H"æfclock-gpt3-mux-fck@1‡Ôti,composite-mux-clock ágpt3_mux_fck‹H"æhclock-gpt4-mux-fck@2‡Ôti,composite-mux-clock ágpt4_mux_fck‹H"æjclock-gpt5-mux-fck@3‡Ôti,composite-mux-clock ágpt5_mux_fck‹H"ælclock-gpt6-mux-fck@4‡Ôti,composite-mux-clock ágpt6_mux_fck‹H"ænclock-gpt7-mux-fck@5‡Ôti,composite-mux-clock ágpt7_mux_fck‹H"æpclock-gpt8-mux-fck@6‡Ôti,composite-mux-clock ágpt8_mux_fck‹H"ærclock-gpt9-mux-fck@7‡Ôti,composite-mux-clock ágpt9_mux_fck‹H"ætgpt2_fckÔti,composite-clock‹efægpt3_fckÔti,composite-clock‹ghgpt4_fckÔti,composite-clock‹ijgpt5_fckÔti,composite-clock‹klgpt6_fckÔti,composite-clock‹mngpt7_fckÔti,composite-clock‹opgpt8_fckÔti,composite-clock‹qrgpt9_fckÔti,composite-clock‹stper_32k_alwon_fckÔfixed-factor-clock‹Htædper_l4_ickÔfixed-factor-clock‹Itæuclock@1010 ti,clksel‡Ô+clock-gpio6-ick@17‡Ôti,omap3-interface-clock ágpio6_ick‹uæ—clock-gpio5-ick@16‡Ôti,omap3-interface-clock ágpio5_ick‹uæ˜clock-gpio4-ick@15‡Ôti,omap3-interface-clock ágpio4_ick‹uæ™clock-gpio3-ick@14‡Ôti,omap3-interface-clock ágpio3_ick‹uæšclock-gpio2-ick@13‡ Ôti,omap3-interface-clock ágpio2_ick‹uæ›clock-wdt3-ick@12‡ Ôti,omap3-interface-clock áwdt3_ick‹uæœclock-uart3-ick@11‡ Ôti,omap3-interface-clock áuart3_ick‹uæclock-uart4-ick@18‡Ôti,omap3-interface-clock áuart4_ick‹uæžclock-gpt9-ick@10‡ Ôti,omap3-interface-clock ágpt9_ick‹uæŸclock-gpt8-ick@9‡ Ôti,omap3-interface-clock ágpt8_ick‹uæ clock-gpt7-ick@8‡Ôti,omap3-interface-clock ágpt7_ick‹uæ¡clock-gpt6-ick@7‡Ôti,omap3-interface-clock ágpt6_ick‹uæ¢clock-gpt5-ick@6‡Ôti,omap3-interface-clock ágpt5_ick‹uæ£clock-gpt4-ick@5‡Ôti,omap3-interface-clock ágpt4_ick‹uæ¤clock-gpt3-ick@4‡Ôti,omap3-interface-clock ágpt3_ick‹uæ¥clock-gpt2-ick@3‡Ôti,omap3-interface-clock ágpt2_ick‹uæ¦clock-mcbsp2-ick@0‡Ôti,omap3-interface-clock ámcbsp2_ick‹uæ§clock-mcbsp3-ick@1‡Ôti,omap3-interface-clock ámcbsp3_ick‹uæ¨clock-mcbsp4-ick@2‡Ôti,omap3-interface-clock ámcbsp4_ick‹uæ©emu_src_ckÔti,clkdm-gate-clock‹væ*secure_32k_fckÔ fixed-clock5€æwgpt12_fckÔfixed-factor-clock‹wtæwdt1_fckÔfixed-factor-clock‹wtsecurity_l4_ick2Ôfixed-factor-clock‹Itæxclock@a14 ti,clksel‡ Ô+clock-aes1-ick@3‡Ôti,omap3-interface-clock áaes1_ick‹xæclock-rng-ick@2‡Ôti,omap3-interface-clockárng_ick‹xæûclock-sha11-ick@1‡Ôti,omap3-interface-clock ásha11_ick‹xclock-des1-ick@0‡Ôti,omap3-interface-clock ádes1_ick‹xclock-pka-ick@4‡Ôti,omap3-interface-clockápka_ick‹yclock@f00 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?ÿÿÿÿopp-supplyti,omap-opp-supply \ûthermal-zonescpu-thermal wú è ›N  ¨tripscpu_alert ¸8€ ÄЂpassiveæcpu_crit ¸_ ÄÐ ‚criticalcooling-mapsmap0 Ï Ôÿÿÿÿÿÿÿÿmemory@80000000{memory‡€leds gpio-ledsŸdefault­ledb „cm-t3x:green ã  éheartbeathsusb1_power_regregulator-fixed •hsusb1_vbus¤2Z ¼2Z  ÿpæhsusb2_power_regregulator-fixed •hsusb2_vbus¤2Z ¼2Z  ÿpæhsusb1_phyusb-nop-xceivá5 æhsusb2-phy-pinsusb-nop-xceivá5 æads7846-regregulator-fixed •ads7846-reg¤2Z ¼2Z æñsvideo-connectorsvideo-connector„tvportendpoint Ÿæsoundti,omap-twl4030 cm-t35 %regulator-vddvarioregulator-fixed •vddvario .æregulator-vdd33aregulator-fixed•vdd33a .æwl12xx_vmmc2regulator-fixed•vw1271Ÿdefault­ ¤w@¼w@ !  ÿN  Bæ÷wl12xx_vaux2regulator-fixed•vwl1271_vaux2¤w@¼w@ U"æø compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypass#ssize-cellsti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0pagesizebci3v1-supplyio-channelsio-channel-namesti,use-ledsti,pullupsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplyvqmmc-supplynon-removablecap-power-off-cardref-clock-frequencystatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdda-supplyremote-endpointti,channelsti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicegpioslinux,default-triggerstartup-delay-usreset-gpiosti,modelti,mcbspregulator-always-onenable-active-highvin-supply