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cpusmarvell,armada-380-smpcpu@0ncpu!arm,cortex-a9¢cpu@1ncpu!arm,cortex-a9¢chosen serial1:115200n8memorynmemory¢@ #address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatusdevbus,bus-widthdevbus,turn-off-psdevbus,badr-skew-psdevbus,acc-first-psdevbus,acc-next-psdevbus,rd-setup-psdevbus,rd-hold-psdevbus,sync-enabledevbus,wr-high-psdevbus,wr-low-psdevbus,ale-wr-psbank-widthlabelcache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandlepinctrl-namespinctrl-0clock-frequencypinctrl-1scl-gpiosda-gpioi2c-mux-idle-disconnectgpio-controller#gpio-cellsreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpiosgpio-ranges#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitdmacap,memcpydmacap,xordmacap,memsetmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesnand-rbnand-on-flash-bbtnand-ecc-strengthnand-ecc-step-sizemarvell,nand-enable-arbitermrvl,clk-delay-cycles#sound-dai-cellsno-memory-wccell-indexspi-max-frequencydevice_typemsi-parentbus-rangeassigned-addressesinterrupt-namesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-lanereset-gpiosreset-delay-usenable-methodstdout-path