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1disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartþµÒM+¯ baudclkapb_pclk4- - 9txrxa±kdefaultMC1okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartþ¶ÒN+³¡baudclkapb_pclk4- - 9txrxa²kdefaultMC 1disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartþ·ÒO+·¢baudclkapb_pclk4  9txrxa³kdefaultMC 1disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartþ¸ÒP+»£baudclkapb_pclk4  9txrxa´kdefaultMC 1disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartþ¹ÒQ+¿¤baudclkapb_pclk4 9txrxaµkdefaultMC1okayserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartþºÒR+Ã¥baudclkapb_pclk4gg9txrxa¶kdefaultMC1okayserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartþ»ÒS+Ǧbaudclkapb_pclk4g g 9txrxa·kdefaultMC 1disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartþ¼ÒT+˧baudclkapb_pclk4g g 9txrxa¸kdefaultMC 1disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½+LK pwmpclka¹kdefaultZ 1disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½+LK pwmpclkaºkdefaultZ 1disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½ +LK pwmpclka»kdefaultZ 1disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½0+LK pwmpclka¼kdefaultZ 1disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾+ON pwmpclka½kdefaultZ 1disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾+ON pwmpclka¾kdefaultZ 1disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾ +ON pwmpclka¿kdefaultZ 1disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾0+ON pwmpclkaÀkdefaultZ 1disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿+RQ pwmpclkaÁkdefaultZ 1disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿+RQ pwmpclkaÂkdefaultZ 1disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿ +RQ pwmpclkaÃkdefaultZ 1disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿0+RQ pwmpclkaÄkdefaultZ 1disabledthermal-zonespackage-thermal ü  Åtripspackage-crit 0Á8 <� criticalbigcore0-thermal üd  Åtripsbigcore0-alert 0L <�ÐpassiveÆbigcore0-crit 0Á8 <� criticalcooling-mapsmap0 GÆ Lÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿbigcore2-thermal üd  Åtripsbigcore2-alert 0L <�ÐpassiveÇbigcore2-crit 0Á8 <� criticalcooling-mapsmap0 GÇ Lÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlittlecore-thermal üd  Åtripslittlecore-alert 0L <�ÐpassiveÈlittlecore-crit 0Á8 <� criticalcooling-mapsmap0 GÈ0 Lÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcenter-thermal ü  Åtripscenter-crit 0Á8 <� criticalgpu-thermal üd  Åtripsgpu-alert 0L <�ÐpassiveÉgpu-crit 0Á8 <� criticalcooling-mapsmap0 GÉ LÊÿÿÿÿÿÿÿÿnpu-thermal ü  Åtripsnpu-crit 0Á8 <� criticaltsadc@fec00000rockchip,rk3588-tsadcþÀҍ+žtsadcapb_pclk2žB„€XVW2tsadc-apbtsadc [ÔÀ r ‰aË ¤Ì kgpiootpout ®1okayÅadc@fec10000rockchip,rk3588-saradcþÁÒŽ Ä+‘saradcapb_pclkXU 2saradc-apb 1disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cþÈ+ˆ€ i2cpclkÒCaÍkdefault+1okayrtc@51haoyu,hym8563Q ¦Ò¸íhym8563kdefaultaÎ Öi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cþÉ+‰ i2cpclkÒDaÏkdefault+ 1disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2cþÊ+Š‚ i2cpclkÒEaÐkdefault+ 1disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiþËÒJ+›–spiclkapb_pclk4g g9txrx˜ aÑÒÓkdefault+ 1disabledefuse@fecc0000rockchip,rk3588-otpþÌ +Œ‹otpapb_pclkphyarbX§¦¨ 2otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c änpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecellþÑ@ ÒZ[v+p apb_pclkgphy@fed60000rockchip,rk3588-hdptx-phyþÖ + Trefapb>8X#cde!""2phyapbinitcmnlaneroplllcpllTÔ 1disabledphy@fed80000rockchip,rk3588-usbdp-phyþØ>+¡lVÕrefclkimmortalpclkutmi(X   2initcmnlanepcs_apbpma_apb éÖ ü× Ø #Ù 1disabled#phy@fee00000rockchip,rk3588-naneng-combphyþà+¨vW refapbpipe2¨Bõá>X<�C2phyapb 3+ EÚ1okaylphy@fee20000rockchip,rk3588-naneng-combphyþâ+ªxW refapbpipe2ªBõá>X>E2phyapb 3+ EÛ1okay(sram@ff001000 mmio-sramÿðÿð+pinctrlrockchip,rk3588-pinctrlTÜ+Ýgpio@fd8a0000rockchip,gpio-bankýŠÒ+qr ‚ [Ý V ’ò¦gpio@fec20000rockchip,gpio-bankþÂÒ+st ‚ [Ý V ’ògpio@fec30000rockchip,gpio-bankþÃÒ+uv ‚ [Ý@ V ’òþgpio@fec40000rockchip,gpio-bankþÄÒ+wx ‚ [Ý` V ’ògpio@fec50000rockchip,gpio-bankþÅÒ+yz ‚ [Ý€ V ’òëpcfg-pull-up gâpcfg-pull-down tàpcfg-pull-none ƒÞpcfg-pull-none-drv-level-2 ƒ äpcfg-pull-up-drv-level-1 g ãpcfg-pull-up-drv-level-2 g ßpcfg-pull-none-smt ƒ Ÿáauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout ´Þwemmc-bus8€ ´ßßßßßßßßxemmc-clk ´ßyemmc-cmd ´ßzemmc-data-strobe ´à{eth1fspigmac1gpuhdmii2c0i2c0m2-xfer ´áá,i2c1i2c1m0-xfer ´ á á™i2c2i2c2m0-xfer ´ á áši2c3i2c3m0-xfer ´ á á›i2c4i2c4m0-xfer ´ á áœi2c5i2c5m0-xfer ´ á ái2c6i2c6m0-xfer ´ á áÍi2c7i2c7m0-xfer ´ á áÏi2c8i2c8m0-xfer ´ á áÐi2s0i2s0-lrck ´Þ|i2s0-sclk ´Þ}i2s0-sdi0 ´Þ~i2s0-sdi1 ´Þi2s0-sdi2 ´Þ€i2s0-sdi3 ´Þi2s0-sdo0 ´Þ‚i2s0-sdo1 ´Þƒi2s0-sdo2 ´Þ„i2s0-sdo3 ´Þ…i2s1i2s1m0-lrck ´Þ†i2s1m0-sclk ´Þ‡i2s1m0-sdi0 ´Þˆi2s1m0-sdi1 ´Þ‰i2s1m0-sdi2 ´ÞŠi2s1m0-sdi3 ´Þ‹i2s1m0-sdo0 ´ ÞŒi2s1m0-sdo1 ´ ލi2s1m0-sdo2 ´ ÞŽi2s1m0-sdo3 ´ ޏi2s2i2s2m1-lrck ´Þ‘i2s2m1-sclk ´ Þ’i2s2m1-sdi ´ Þ“i2s2m1-sdo ´ Þ”i2s3i2s3-lrck ´Þ•i2s3-sclk ´Þ–i2s3-sdi ´Þ—i2s3-sdo ´Þ˜jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp ´âÞÞÞÞÞÞ§pmupwm0pwm0m0-pins ´Þ/pwm1pwm1m0-pins ´Þ0pwm2pwm2m1-pins ´ Þ1pwm3pwm3m0-pins ´Þ2pwm4pwm4m0-pins ´ Þ¹pwm5pwm5m0-pins ´ Þºpwm6pwm6m0-pins ´ Þ»pwm7pwm7m0-pins ´ Þ¼pwm8pwm8m0-pins ´ Þ½pwm9pwm9m0-pins ´ Þ¾pwm10pwm10m0-pins ´ Þ¿pwm11pwm11m0-pins ´ ÞÀpwm12pwm12m0-pins ´ ÞÁpwm13pwm13m0-pins ´ ÞÂpwm14pwm14m0-pins ´ ÞÃpwm15pwm15m0-pins ´ ÞÄrefclksatasata0sata1sata2sdiosdiom1-pins` ´ÞÞÞÞÞÞvsdmmcsdmmc-bus4@ ´ßßßßssdmmc-clk ´ßpsdmmc-cmd ´ßqsdmmc-det ´ârspdif0spdif1spi0spi0m0-pins0 ´ããã spi0m0-cs0 ´ãžspi0m0-cs1 ´ãŸspi1spi1m1-pins0 ´ããã£spi1m1-cs0 ´ã¡spi1m1-cs1 ´ã¢spi2spi2m2-pins0 ´ã ãã¥spi2m2-cs0 ´ ã¤spi3spi3m1-pins0 ´ã ãã¯spi3m1-cs0 ´ã­spi3m1-cs1 ´ã®spi4spi4m0-pins0 ´ãããÓspi4m0-cs0 ´ãÑspi4m0-cs1 ´ãÒtsadctsadc-shut ´ÞÌuart0uart0m1-xfer ´â â.uart1uart1m1-xfer ´ â â°uart2uart2m0-xfer ´ â â±uart3uart3m1-xfer ´ â â²uart4uart4m1-xfer ´ â â³uart5uart5m1-xfer ´ â â´uart6uart6m0-xfer ´ â âµuart7uart7m2-xfer ´ â â¶uart8uart8m1-xfer ´ â â·uart9uart9m1-xfer ´ â â¸vopbt656gpio-functsadc-gpio-func ´ÞËeth0gmac0ledsled_user_en ´Þüpcie2pcie2-0-rst ´Þòpcie3pcie3x2-rst ´Þîpcie3x2-vcc3v3-en ´Þÿpcie3x4-rst ´Þêpcie3x4-vcc3v3-en ´Þhym8563hym8563-int ´ÞÎusbvcc5v0-host-en ´Þusb@fc400000rockchip,rk3588-dwc3snps,dwc3ü@@ÒÝ+—–•ref_clksuspend_clkbus_clk8otg @åæEusb2-phyusb3-phy Outmi_wide# XS_§Èé 1disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsysconý[€ûsyscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsysconý\úsyscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsysconý\À@ùsyscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdý]@@+øusb2phy@4000rockchip,rk3588-usb2phy@¸+ phyclk íusb480m_phy1ÒŠXn2phyapb 1disabled÷otg-port> 1disabledåi2s@fddc8000rockchip,rk3588-i2s-tdmýÜ€Ò¼+ññîmclk_txmclk_rxhclk2ïÀ4g9tx# Xº2tx-m× 1disabledi2s@fddf4000rockchip,rk3588-i2s-tdmýß@Òº+99?mclk_txmclk_rxhclk26À4g9tx# XÚ2tx-m× 1disabledi2s@fddf8000rockchip,rk3588-i2s-tdmý߀Ò»+++'mclk_txmclk_rxhclk2(À4g9rx# XÇ2rx-m× 1disabledi2s@fde00000rockchip,rk3588-i2s-tdmýàÒ¾+&&"mclk_txmclk_rxhclk2#À4g9rx# Xî2rx-m× 1disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+è0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒsyspmcmsglegacyerrò`çççç$5DèL@é Epcie-phy# "Tððð ð à@ @0 @@þð€dbiapbconfigX&+ 2pwrpipe1okaykdefaultaê Âë Îìlegacy-interrupt-controllerVò Òçpcie-ep@fe150000rockchip,rk3588-pcie-epP @ @þ @ @0€dbidbi2apbaddr_spaceatu0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipeÒ +syspmcmsglegacyerrdma0dma1dma2dma35L@é Epcie-phy# "X&+ 2pwrpipe 1disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+è0+AF<�KPu)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒÿþsyspmcmsglegacyerrò`íííí$5DèL@é Epcie-phy# "Tñññ ñ à@ @@0 @@@þñ€dbiapbconfigX', 2pwrpipe1okaykdefaultaî Âë Îïlegacy-interrupt-controllerVò Òÿípcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcieè /0+BG=LQ¯)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒóòñðïsyspmcmsglegacyerrò`ðððð$5D j L@ñ Epcie-phy# "Tòòò ò à@ €@0 @€@þò€dbiapbconfigX(- 2pwrpipe+1okaykdefaultaò Âë Îólegacy-interrupt-controllerVò Òððethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20aþ Òãâmacirqeth_wake_irq(+67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref# !X# 2stmmacethTck+|ôŒõ°öà 1disabledmdiosnps,dwmac-mdio+stmmac-axi-configÌÖæôrx-queues-configöõqueue0queue1tx-queues-config öqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciþ"Ò(+c`fUpsatapmaliverxoobrefasic"+ 1disabledsata-port@04@@ñ Esata-phyA P phy@fed90000rockchip,rk3588-usbdp-phyþÙ>+¡mW÷refclkimmortalpclkutmi(X2initcmnlanepcs_apbpma_apb éø ü× ù #Ù 1disabledæphy@fee10000rockchip,rk3588-naneng-combphyþá+©wW refapbpipe2©Bõá>X=D2phyapb 3+ Eú1okayñphy@fee80000rockchip,rk3588-pcie3-phyþè>+ypclkXH2phy 3+ Þû1okayéopp-table-cluster0operating-points-v2 ï opp-1008000000 ú<Ü  L¸ L¸~ð œ@opp-1200000000 úG†Œ  ß4 ß4~ð œ@opp-1416000000 úTfr  ¢„ ¢„~ð œ@ opp-1608000000 ú_Ø"  øP øP~ð œ@opp-1800000000 úkIÒ ~ð~ð~ð œ@opp-table-cluster1operating-points-v2 ïopp-1200000000 úG†Œ  L¸ L¸B@ œ@opp-1416000000 úTfr   B@ œ@opp-1608000000 ú_Ø"  ¢„ ¢„B@ œ@opp-1800000000 úkIÒ  øP øPB@ œ@opp-2016000000 úx)¸ HHB@ œ@opp-2208000000 úƒ›h llB@ œ@opp-2400000000 ú  B@B@B@ œ@opp-table-cluster2operating-points-v2 ïopp-1200000000 úG†Œ  L¸ L¸B@ œ@opp-1416000000 úTfr   B@ œ@opp-1608000000 ú_Ø"  ¢„ ¢„B@ œ@opp-1800000000 úkIÒ  øP øPB@ œ@opp-2016000000 úx)¸ HHB@ œ@opp-2208000000 úƒ›h llB@ œ@opp-2400000000 ú  B@B@B@ œ@opp-tableoperating-points-v2!opp-300000000 úᣠ L¸ L¸ øPopp-400000000 úׄ  L¸ L¸ øPopp-500000000 úÍe  L¸ L¸ øPopp-600000000 ú#ÃF  L¸ L¸ øPopp-700000000 ú)¹'  ®` ®` øPopp-800000000 ú/¯  q° q° øPopp-900000000 ú5¤é  5 5 øPopp-1000000000 ú;šÊ  øP øP øPgpio-leds gpio-ledsled-0 , £heartbeat Ȧ 2heartbeatkdefaultaüvcc12v-dcin-regulatorregulator-fixed –vcc12v_dcin¥¹Ë·ã·ývcc5v0-sys-regulatorregulator-fixed –vcc5v0_sys¥¹ËLK@ãLK@ý)vcc-1v1-nldo-s3-regulatorregulator-fixed–vcc_1v1_nldo_s3¥¹ËÈàãÈà)¬chosen Hserial2:1500000n8vcc3v3-pcie2x1l0-regulatorregulator-fixed–vcc3v3_pcie2x1l0Ë2Z ã2Z  Tˆtóvcc3v3-pcie3x2-regulatorregulator-fixed e Èþkdefaultaÿ–vcc3v3_pcie3x2Ë2Z ã2Z  Tˆ)ïvcc3v3-pcie3x4-regulatorregulator-fixed e Èþkdefaulta–vcc3v3_pcie3x4Ë2Z ã2Z  Tˆ)ìvcc5v0-host-regulatorregulator-fixed e xkdefaulta –vcc5v0_hostËLK@ãLK@¹¥)* compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellswakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsreset-gpiosvpcie3v3-supplyrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendcolorlinux,default-triggerstdout-pathstartup-delay-usenable-active-highgpio