Ð þíè%8Ùt(±Ù<� ,anbernic,rg503rockchip,rk35667handsetDAnbernic RG503aliasesJ/pinctrl/gpio@fdd60000P/pinctrl/gpio@fe740000V/pinctrl/gpio@fe750000\/pinctrl/gpio@fe760000b/pinctrl/gpio@fe770000h/i2c@fdd40000m/i2c@fe5a0000r/i2c@fe5b0000w/i2c@fe5c0000|/i2c@fe5d0000/i2c@fe5e0000†/serial@fdd50000Ž/serial@fe650000–/serial@fe660000ž/serial@fe670000¦/serial@fe680000®/serial@fe690000¶/serial@fe6a0000¾/serial@fe6b0000Æ/serial@fe6c0000Î/serial@fe6d0000Ö/spi@fe610000Û/spi@fe620000à/spi@fe630000å/spi@fe640000ê/mmc@fe2b0000ï/mmc@fe2c0000ô/mmc@fe000000cpus cpu@0ùcpu,arm,cortex-a55 psci-A€N@`€m€z@Œ€™ªµ cpu@100ùcpu,arm,cortex-a55psci-A€N@`€m€z@Œ€™ªµ cpu@200ùcpu,arm,cortex-a55psci-A€N@`€m€z@Œ€™ªµ cpu@300ùcpu,arm,cortex-a55psci-A€N@`€m€z@Œ€™ªµ l3-cache,cache½ÉCP@bµopp-table-0,operating-points-v2×µopp-408000000âQ– é »  » Œ0÷œ@opp-600000000â#ÃF é »  » Œ0opp-816000000â0£, é »  » Œ0opp-1104000000âAÍ´ é »  » Œ0opp-1416000000âTfr é »  » Œ0opp-1608000000â_Ø" éà˜à˜Œ0opp-1800000000âkIÒ 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Mutmi_wide7V•]‚okayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF “ ‹ ±ýA»(Ƶusb@fd800000 ,generic-ehciý€ “‚ ½¾¼usb ‚disabledusb@fd840000 ,generic-ohciý„ “ƒ ½¾¼usb ‚disabledusb@fd880000 ,generic-ehciýˆ “… ¿À¼usb‚okayusb@fd8c0000 ,generic-ohciýŒ “† ¿À¼usb‚okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýµ\io-domains&,rockchip,rk3568-pmu-io-voltage-domain‚okayÕãñÿ )7syscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsysconµ§syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƵsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȵ¨syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɵ©syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€µªsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€µ«clock-controller@fdd00000,rockchip,rk3568-pmucruýÐ+Eµclock-controller@fdd20000,rockchip,rk3568-cruýÒ  xin24m+E Rb€G†Œ ëÂÍewŽµi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ “. -  i2cpclkë õdefault ‚okaypmic@20,rockchip,rk817 !“Ørk808-clkout1rk808-clkout2 mclk HRHw–+›õdefaultë"#¬º$Æ$Ò$Þ$ê$ö$$$%µ¾regulatorsDCDC_REG1&:L¡ d™p|q‘ ¨vdd_logicregulator-state-mem·Ð » DCDC_REG2&:L¡ d™p|q‘¨vdd_gpuµEregulator-state-mem·DCDC_REG3&:‘¨vcc_ddrregulator-state-memìDCDC_REG4&:L2Z d2Z ‘¨vcc_3v3µregulator-state-memìÐ2Z LDO_REG1&:Lw@dw@ ¨vcca1v8_pmuµMregulator-state-memìÐw@LDO_REG2&:L » d »  ¨vdda_0v9regulator-state-mem·LDO_REG3&:L » d »  ¨vdda0v9_pmuregulator-state-memìÐ » LDO_REG4&:L2Z d2Z  ¨vccio_acodecµregulator-state-mem·LDO_REG5&:Lw@d2Z  ¨vccio_sdµregulator-state-mem·LDO_REG6&:L2Z d2Z  ¨vcc3v3_pmuµregulator-state-memìÐ2Z LDO_REG7&:Lw@dw@¨vcc_1v8µregulator-state-mem·LDO_REG8&:Lw@d2Z  ¨vcc1v8_dvpµregulator-state-mem·LDO_REG9&:L*¹€d*¹€ ¨vcc2v8_dvpregulator-state-mem·BOOST&:LG·`dReÀ¨boostµ%regulator-state-mem·OTG_SWITCH ¨otg_switchregulator-state-mem·charger&'9“à_† regulator@40 ,fcs,fan53555@†&:L ß4d5°¨vdd_cpu|ü£$µregulator-state-mem·serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ “t  , baudclkapb_pclk®''ë(õdefault³À ‚disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkë)õdefaultÊ‚okayµ½pwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkë*õdefaultÊ ‚disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0  pwmpclkë+õdefaultÊ ‚disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0  pwmpclkë,õdefaultÊ ‚disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerÕ µpower-domain@7 é-Õpower-domain@8 ÌÍ é./0Õpower-domain@9  ÚÛÜ é123Õpower-domain@10  ñòé456789Õpower-domain@11  íé:Õpower-domain@13  é;Õpower-domain@14  é<�=>Õpower-domain@15 é?@ABCÕgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$“()' ðjobmmugpu  gpubus-D7‚okayEµ˜video-codec@fdea0400,rockchip,rk3568-vpuýê “‹ðvdpu îï  aclkhclk F7 iommu@fdea0800,rockchip,rk3568-iommuýê@ “Š  aclkiface îï7 µFrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ “Z óôõ aclkhclksclkV&$%  coreaxiahb7 video-codec@fdee0000,rockchip,rk3568-vepuýî “@ ýþ  aclkhclk G7 iommu@fdee0800,rockchip,rk3568-iommuýî@ “? ýþ  aclkiface7 µGmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ “d  ÁÂŽ biuciuciu-driveciu-sample,7ðÑ€Vë reset‚okayEO`mƒHŽ•› ëIJKõdefault©¶LÂMethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ“ ðmacirqeth_wake_irq@ †‰‰ÇÃĉÈW stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refVì  stmmacethŽÏNßðOP ‚disabledmdio,snps,dwmac-mdio stmmac-axi-config)9µNrx-queues-configIµOqueue0tx-queues-config_µPqueue0vop@fe040000 þ0þ@uvopgamma-lut “”( ÝÞßàá% aclkhclkdclk_vp0dclk_vp1dclk_vp2 Q7 Ž‚okay,rockchip,rk3566-vopRßàwports µport@0 endpoint@2RµZport@1 endpoint@4SµUport@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? “” ÝÞ  aclkiface7 ‚okayµQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ “D pclk èdphyT7  apbVŽ‚okayports port@0endpointUµSport@1endpointVµÈdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ “E pclk édphyW7  apbVŽ ‚disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  “-( æç“(Ú iahbisfrcecrefõdefaultëX7 ³Ž›‚okayYµports port@0endpointZµRport@1endpoint[µºqos@fe128000,rockchip,rk3568-qossysconþ€ µ-qos@fe138080,rockchip,rk3568-qossysconþ€€ µ<�qos@fe138100,rockchip,rk3568-qossysconþ µ=qos@fe138180,rockchip,rk3568-qossysconþ€ µ>qos@fe148000,rockchip,rk3568-qossysconþ€ µ.qos@fe148080,rockchip,rk3568-qossysconþ€€ µ/qos@fe148100,rockchip,rk3568-qossysconþ µ0qos@fe150000,rockchip,rk3568-qossysconþ µ:qos@fe158000,rockchip,rk3568-qossysconþ€ µ4qos@fe158100,rockchip,rk3568-qossysconþ µ5qos@fe158180,rockchip,rk3568-qossysconþ€ µ6qos@fe158200,rockchip,rk3568-qossysconþ‚ µ7qos@fe158280,rockchip,rk3568-qossysconþ‚€ µ8qos@fe158300,rockchip,rk3568-qossysconþƒ µ9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ µ?qos@fe190280,rockchip,rk3568-qossysconþ€ µ@qos@fe190300,rockchip,rk3568-qossysconþ µAqos@fe190380,rockchip,rk3568-qossysconþ€ µBqos@fe190400,rockchip,rk3568-qossysconþ µCqos@fe198000,rockchip,rk3568-qossysconþ€ µ;qos@fe1a8000,rockchip,rk3568-qossysconþ€ µ1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ µ2qos@fe1a8100,rockchip,rk3568-qossysconþ µ3dfi@fe230000,rockchip,rk3568-dfiþ# “ ›\pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôudbiapbconfig<�“KJIHGðsyspmcmsglegacyerr¨( ‚ƒ„…$ aclk_mstaclk_slvaclk_dbipclkauxùpci ²`Å]]]]Óäó    pcie-phy7Tôôô ô à@@V¡ pipe  ‚disabledlegacy-interrupt-controller ‹ “Hµ]mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ “b  °±Š‹ biuciuciu-driveciu-sample,7ðÑ€VÔ reset‚okayEO #! ,ë^_`aõdefault 7¶Âmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ “c  ²³Œ biuciuciu-driveciu-sample,7ðÑ€VÖ reset‚okayEO #b  ,ëcdefõdefault 7¶Âspi@fe300000 ,rockchip,sfcþ0@ “e xv clk_sfchclk_sfcëgõdefault ‚disabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 “R{}b ëÂn6( |zy{} corebusaxiblocktimer ‚disabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ “4R=AbFÏqFÏq ?C9 mclk_txmclk_rxhclk®h EtxVPQ  tx-mrx-mŽ›‚okayµ i2s@fe410000,rockchip,rk3568-i2s-tdmþA “5REIbFÏqFÏq GK: mclk_txmclk_rxhclk®hh ErxtxVRS  tx-mrx-mŽõdefaultëijkl›‚okay OµÊi2s@fe420000,rockchip,rk3568-i2s-tdmþB “6RMbFÏq OO; mclk_txmclk_rxhclk®hh EtxrxVT tx-mŽõdefaultëmnop› ‚disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC “7 SW<� mclk_txmclk_rxhclk®hh EtxrxVUV  tx-mrx-mŽ› ‚disabledpdm@fe440000,rockchip,rk3568-pdmþD “L ZY pdm_clkpdm_hclk®h  ErxëqrstuvõdefaultVX pdm-m› ‚disabledspdif@fe460000,rockchip,rk3568-spdifþF “f  mclkhclk _\®h Etxõdefaultëw› ‚disableddma-controller@fe530000,arm,pl330arm,primecellþS@“  j    apb_pclk µ'dma-controller@fe550000,arm,pl330arm,primecellþU@“ j    apb_pclk µhi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ “/ HG  i2cpclkëxõdefault  ‚disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ “0 JI  i2cpclkëyõdefault  ‚disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ “1 LK  i2cpclkëzõdefault  ‚disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] “2 NM  i2cpclkë{õdefault  ‚disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ “3 PO  i2cpclkë|õdefault ‚okayµYwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` “•   tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa “g RQ spiclkapb_pclk®'' Etxrxõdefault ë}~  ‚disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb “h TS spiclkapb_pclk®'' Etxrxõdefault 뀁‚  ‚disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc “i VU spiclkapb_pclk®'' Etxrxõdefault 냄…  ‚disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd “j XW spiclkapb_pclk®'' Etxrxõdefault 놇ˆ  ‚disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe “u  baudclkapb_pclk®'' 뉊‹õdefault³À‚okay Œbluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt œŒ ®Œ »Œserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf “v #  baudclkapb_pclk®''ëõdefault³À‚okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg “w '$ baudclkapb_pclk®''ëŽõdefault³À ‚disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh “x +( baudclkapb_pclk®'' ëõdefault³À ‚disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi “y /, baudclkapb_pclk®' ' ëõdefault³À ‚disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj “z 30 baudclkapb_pclk®' ' ë‘õdefault³À ‚disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk “{ 74 baudclkapb_pclk®''ë’õdefault³À ‚disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl “| ;8 baudclkapb_pclk®''ë“õdefault³À ‚disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm “} ?<� baudclkapb_pclk®''ë”õdefault³À ‚disabledthermal-zonescpu-thermal Ëd áè ï•tripscpu_alert0 ÿp Ð?passiveµ–cpu_alert1 ÿ$ø Ð?passivecpu_crit ÿs Ð ?criticalcooling-mapsmap0 –0  ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal Ë áè ï•tripsgpu-threshold ÿp Ð?passivegpu-target ÿ$ø Ð?passiveµ—gpu-crit ÿs Ð ?criticalcooling-mapsmap0 — ˜ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq “sRbf@ ®`  tsadcapb_pclkV‚׎ *sõdefaultsleepë™ Aš K‚okay a xµ•saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr “]  saradcapb_pclkV€  saradc-apb “‚okay ¥µ¶pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkë›õdefaultÊ ‚disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkëœõdefaultÊ‚okayµÂpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY  pwmpclkëõdefaultÊ‚okayµ»pwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY  pwmpclkëžõdefaultÊ‚okayµ¼pwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkëŸõdefaultÊ ‚disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkë õdefaultÊ ‚disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\  pwmpclkë¡õdefaultÊ ‚disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\  pwmpclkë¢õdefaultÊ ‚disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkë£õdefaultÊ ‚disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkë¤õdefaultÊ ‚disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_  pwmpclkë¥õdefaultÊ ‚disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_  pwmpclkë¦õdefaultÊ ‚disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "}  refapbpipeR"bõáVÇ ±§ è Ù‚okayµphy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~  refapbpipeR%bõáVÉ ±§ é Ù ‚disabledµphy@fe870000,rockchip,rk3568-csi-dphyþ‡ y pclk ÙVº apbŽ ‚disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ…  refpclk z Ù7  apbV»‚okayµTmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ†  refpclk { Ù7  apbV¼ ‚disabledµWusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ  phyclkØclk_usbphy0_480m “‡ äª+‚okayµhost-port Ù ‚disabledotg-port Ù‚okayµusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹  phyclkØclk_usbphy1_480m “ˆ ä«+‚okayhost-port Ù‚okayµotg-port Ù ‚disabledµpinctrl,rockchip,rk3568-pinctrlŽ›\ µ¬gpio@fdd60000,rockchip,gpio-bankýÖ “! .  ô ¬  ‹ µ!gpio@fe740000,rockchip,gpio-bankþt “" cd ô ¬  ‹ gpio@fe750000,rockchip,gpio-bankþu “# ef ô ¬@  ‹ µbgpio@fe760000,rockchip,gpio-bankþv “$ gh ô ¬`  ‹ µ¸gpio@fe770000,rockchip,gpio-bankþw “% ij ô ¬€  ‹ µŒpcfg-pull-up µ¯pcfg-pull-none )µ­pcfg-pull-none-drv-level-1 ) 6µ±pcfg-pull-none-drv-level-2 ) 6µ°pcfg-pull-none-drv-level-3 ) 6µ´pcfg-pull-up-drv-level-1  6µ³pcfg-pull-up-drv-level-2  6µ®pcfg-pull-none-smt ) Eµ²pcfg-output-low Zµµacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 e­µcpuebcedpdpemmceth0eth1flashfspifspi-pins` e­­­­­­µggmac0gmac1gpuhdmitxhdmitxm0-cec e­µXi2c0i2c0-xfer e ² ²µ i2c1i2c1-xfer e ² ²µxi2c2i2c2m0-xfer e ²²µyi2c3i2c3m0-xfer e²²µzi2c4i2c4m0-xfer e ² ²µ{i2c5i2c5m1-xfer e²²µ|i2s1i2s1m0-lrcktx e­µji2s1m0-mclk e­µ"i2s1m0-sclktx e­µii2s1m0-sdi0 e ­µki2s1m0-sdo0 e­µli2s2i2s2m0-lrcktx e­µni2s2m0-sclktx e­µmi2s2m0-sdi e­µoi2s2m0-sdo e­µpi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk e­µqpdmm0-clk1 e­µrpdmm0-sdi0 e ­µspdmm0-sdi1 e ­µtpdmm0-sdi2 e ­µupdmm0-sdi3 e­µvpmicpmic-int-l e¯µ#pmupwm0pwm0m1-pins e­µ)pwm1pwm1m0-pins e­µ*pwm2pwm2m0-pins e­µ+pwm3pwm3-pins e­µ,pwm4pwm4-pins e­µ›pwm5pwm5-pins e­µœpwm6pwm6-pins e­µpwm7pwm7-pins e­µžpwm8pwm8m0-pins e ­µŸpwm9pwm9m0-pins e ­µ pwm10pwm10m0-pins e ­µ¡pwm11pwm11m0-pins e­µ¢pwm12pwm12m0-pins e­µ£pwm13pwm13m0-pins e­µ¤pwm14pwm14m0-pins e­µ¥pwm15pwm15m0-pins e­µ¦refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ e®®®®µ^sdmmc0-clk e®µ_sdmmc0-cmd e®µ`sdmmc0-det e¯µasdmmc1sdmmc1-bus4@ e®®®®µcsdmmc1-clk e®µesdmmc1-cmd e®µdsdmmc1-det e ¯µfsdmmc2sdmmc2m0-bus4@ e®®®®µIsdmmc2m0-clk e®µKsdmmc2m0-cmd e®µJspdifspdifm0-tx e­µwspi0spi0m0-pins0 e ­­­µspi0m0-cs0 e­µ}spi0m0-cs1 e­µ~spi1spi1m0-pins0 e ­­­µ‚spi1m0-cs0 e­µ€spi1m0-cs1 e­µspi2spi2m0-pins0 e­­­µ…spi2m0-cs0 e­µƒspi2m0-cs1 e­µ„spi3spi3m0-pins0 e ­­ ­µˆspi3m0-cs0 e­µ†spi3m0-cs1 e­µ‡tsadctsadc-shutorg e­µ™tsadc-pin e­µšuart0uart0-xfer e¯¯µ(uart1uart1m1-xfer e¯¯µ‰uart1m1-ctsn e­µŠuart1m1-rtsn e­µ‹uart2uart2m0-xfer e¯¯µuart3uart3m0-xfer e¯¯µŽuart4uart4m0-xfer e¯¯µuart5uart5m0-xfer e¯¯µuart6uart6m0-xfer e¯¯µ‘uart7uart7m0-xfer e¯¯µ’uart8uart8m0-xfer e¯¯µ“uart9uart9m0-xfer e¯¯µ”vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-btnsbtn-pins-ctrl e¯¯¯¯¯¯ ¯ ¯ ¯ ¯ ¯¯¯¯¯¯µ·btn-pins-vol e¯¯µ¹joy-muxjoy-mux-en e µµÄsdio-pwrseqwifi-enable-h e­µ¿vcc3v3-lcdvcc-lcd-h e­µÀvcc-wifivcc-wifi-h e­µÁaudio-amplifierspk-amp-enable-h e­µËgpio-lcdlcd-reset e­µÇgpio-spispi-pins0 e­­ ­µÆchosen sserial2:1500000n8adc-keys ,adc-keys ¶ ‹buttons œw@ ¶<�button-mode ÄMODE Ê<� ÕÖgpio-keys-control ,gpio-keysë·õdefaultbutton-b &¸ ÄSOUTH Ê0button-down &¸ ÄDPAD-DOWN Ê!button-l1 &¸  ÄTL Ê6button-l2 &¸  ÄTL2 Ê8button-select &¸ ÄSELECT Ê:button-start &¸  ÄSTART Ê;button-up &¸ ÄDPAD-UP Ê button-x &¸ ÄNORTH Ê3button-a &¸ ÄEAST Ê1button-left &¸ ÄDPAD-LEFT Ê"button-right &¸ ÄDPAD-RIGHT Ê#button-r1 &¸  ÄTR Ê7button-r2 &¸  ÄTR2 Ê9button-thumbl &¸ ÄTHUMBL Ê=button-thumbr &¸ ÄTHUMBR Ê>button-y &¸ ÄWEST Ê4gpio-keys-vol ,gpio-keys ïë¹õdefaultbutton-vol-down &¸ ÄVOLUMEDOWN Êrbutton-vol-up &¸ ÄVOLUMEUP Êshdmi-con,hdmi-connectorY?cportendpointºµ[pwm-leds ,pwm-ledsled-0 ú on power ÿ &»a¨led-1 ú charging ÿ &¼a¨led-2 ú off status ÿ &½a¨sdio-pwrseq,mmc-pwrseq-simple ¾  ext_clockë¿õdefault +È BŒµHregulator-vcc3v3-lcd0,regulator-fixed N! SëÀõdefault:L2Z d2Z ¨vcc3v3_lcd0_n£regulator-state-mem·regulator-vcc-sys,regulator-fixed&:L9ûÀd9ûÀ¨vcc_sysµ$regulator-vcc-wifi,regulator-fixed S N!ëÁõdefault&:L2Z d2Z  ¨vcc_wifiµLpwm-vibrator ,pwm-vibrator fenable &Â;šÊadc-joystick ,adc-joystick ÃÃÃÃëÄõdefault ¶<� axis@0 p  y  ‚ÿ Êaxis@1 p  y  ‚ÿ Êaxis@2 p  y  ‚ÿ Êaxis@3 p  y  ‚ÿ Êadc-mux,io-channel-mux ‚left_xright_xleft_yright_y “ ¶ ‹parent ŒÅ ™dµÃbattery,simple-battery ¨4ú€ Ê“à ç„€ @@ 2É Y?¨à v3á@ “¨ ¨?¨àd=Ûð_<Ê€Z;çðU;ÐP:aPK9¹XF9(ÐA8«Ð<�82¸77±Ð27[à-7`(6î€#6»¸6}8635Ɉ5H  4”ð3á@µ&mux-controller ,gpio-mux ½!! ǵÅspi ,spi-gpioõdefaultëÆ  ÚŒ  äŒ ïŒ øpanel@0,samsung,ams495qa01õdefaultëÇ BŒportendpointȵVsound,simple-audio-card 8rk817_extÉOi2s .ŒhCLMicrophoneMic JackHeadphoneHeadphonesSpeakerInternal SpeakersžfMICLMic JackHeadphonesHPOLHeadphonesHPORInternal SpeakersSpeaker Amp OUTLInternal SpeakersSpeaker Amp OUTRSpeaker Amp INLHPOLSpeaker Amp INRHPOR€Internal Speakerssimple-audio-card,codec‰¾simple-audio-card,cpu‰Êaudio-amplifier,simple-audio-amplifier ®ŒëËõdefault ŸSpeaker AmpµÉ interrupt-parent#address-cells#size-cellscompatiblechassis-typemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr50vmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointddc-i2c-busrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpsd-uhs-sdr104dma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltautorepeatcolordefault-statefunctionmax-brightnesspwmspost-power-on-delay-msreset-gpiosgpioenable-active-highpwm-namesabs-flatabs-fuzzabs-rangemux-controlssettle-time-uscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0mux-gpios#mux-control-cellssck-gpiosmosi-gpioscs-gpiosnum-chipselectsvdd-supplysimple-audio-card,aux-devssimple-audio-card,hp-det-gpiosimple-audio-card,widgetssimple-audio-card,routingsimple-audio-card,pin-switchessound-name-prefix