Ð þíéã8ÛL(—Û  ,anbernic,rg353vrockchip,rk35667handsetDAnbernic RG353ValiasesJ/pinctrl/gpio@fdd60000P/pinctrl/gpio@fe740000V/pinctrl/gpio@fe750000\/pinctrl/gpio@fe760000b/pinctrl/gpio@fe770000h/i2c@fdd40000m/i2c@fe5a0000r/i2c@fe5b0000w/i2c@fe5c0000|/i2c@fe5d0000/i2c@fe5e0000†/serial@fdd50000Ž/serial@fe650000–/serial@fe660000ž/serial@fe670000¦/serial@fe680000®/serial@fe690000¶/serial@fe6a0000¾/serial@fe6b0000Æ/serial@fe6c0000Î/serial@fe6d0000Ö/spi@fe610000Û/spi@fe620000à/spi@fe630000å/spi@fe640000ê/mmc@fe310000ï/mmc@fe2b0000ô/mmc@fe2c0000ù/mmc@fe000000cpus cpu@0þcpu,arm,cortex-a55 $psci2F€S@e€r€@‘€ž¯º cpu@100þcpu,arm,cortex-a55 $psci2F€S@e€r€@‘€ž¯º cpu@200þcpu,arm,cortex-a55 $psci2F€S@e€r€@‘€ž¯º cpu@300þcpu,arm,cortex-a55 $psci2F€S@e€r€@‘€ž¯º l3-cache,cacheÂÎHU@gºopp-table-0,operating-points-v2ܺopp-408000000çQ– î »  » Œ0üœ@opp-600000000ç#ÃF î »  » Œ0opp-816000000ç0£, î »  » Œ0 opp-1104000000çAÍ´ î »  » Œ0opp-1416000000çTfr î »  » Œ0opp-1608000000ç_Ø" îà˜à˜Œ0opp-1800000000çkIÒ îŒ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc‚* protocol@14 0ºopp-table-1,operating-points-v2ºDopp-200000000ç ë î øP øPB@opp-300000000çᣠî øP øPB@opp-400000000çׄ î øP øPB@opp-600000000ç#ÃF î »  » B@opp-700000000ç)¹' î~ð~ðB@opp-800000000ç/¯ îB@B@B@hdmi-sound,simple-audio-card=HDMITi2sm‡okaysimple-audio-card,codecŽsimple-audio-card,cpuŽ pmu,arm,cortex-a55-pmu0˜äåæç£ psci ,arm,psci-1.0+smctimer,arm,armv8-timer0˜   ¶xin24m ,fixed-clockÍn6Ýxin24m0ºxin32k ,fixed-clockÍ€Ýxin32kðúdefault0sram@10f000 ,mmio-sram ð ðsram@0,arm,scmi-shmem ºsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ü@›œsatapmaliverxoob ˜_  sata-phy*<� ‡disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ü€ ¡¢satapmaliverxoob ˜`  sata-phy*<� ‡disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3 üÀ@ ˜©¦§¥ref_clksuspend_clkbus_clk Jperipheral Rutmi_wide<�[”b‡okay  usb2-phy{ ‚high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3 ý@ ˜ª©ª¨ref_clksuspend_clkbus_clkJhost  usb2-phyusb3-phy Rutmi_wide<�[•b‡okayinterrupt-controller@fd400000 ,arm,gic-v3  ý@ýF ˜ ¥¶ýAÀ(˺usb@fd800000 ,generic-ehci ý€ ˜‚½¾¼ usb ‡disabledusb@fd840000 ,generic-ohci ý„ ˜ƒ½¾¼ usb ‡disabledusb@fd880000 ,generic-ehci ýˆ ˜…¿À¼ usb‡okayusb@fd8c0000 ,generic-ohci ýŒ ˜†¿À¼ usb‡okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd ýºaio-domains&,rockchip,rk3568-pmu-io-voltage-domain‡okayÚèö .<�syscon@fdc50000 ýÅ ,rockchip,rk3566-pipe-grfsysconº±syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd ýƺsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsyscon ýȺ²syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsyscon ýɺ³syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsyscon ýÊ€º´syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsyscon ýÊ€€ºµclock-controller@fdd00000,rockchip,rk3568-pmucru ýÐ0Jºclock-controller@fdd20000,rockchip,rk3568-cru ýÒxin24m0J Wg€G†Œ ëÂdÿ`|“ºi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c ýÔ ˜.- i2cpclkð údefault ‡okaypmic@20,rockchip,rk817 !˜Ýrk808-clkout1rk808-clkout2mclkHWH|–0 údefaultð"#±¿$Ë$×$ã$ï$û$$$%ºÈregulatorsDCDC_REG1+?Q¡ i™pq– ­vdd_logicregulator-state-mem¼Õ » DCDC_REG2+?Q¡ i™pq–­vdd_gpuºEregulator-state-mem¼DCDC_REG3+?–­vcc_ddrregulator-state-memñDCDC_REG4+?Q2Z i2Z –­vcc_3v3ºregulator-state-memñÕ2Z LDO_REG1+?Qw@iw@ ­vcca1v8_pmuºMregulator-state-memñÕw@LDO_REG2+?Q » i »  ­vdda_0v9regulator-state-mem¼LDO_REG3+?Q » i »  ­vdda0v9_pmuregulator-state-memñÕ » LDO_REG4+?Q2Z i2Z  ­vccio_acodecºregulator-state-mem¼LDO_REG5+?Qw@i2Z  ­vccio_sdºregulator-state-mem¼LDO_REG6+?Q2Z i2Z  ­vcc3v3_pmuºregulator-state-memñÕ2Z LDO_REG7+?Qw@iw@­vcc_1v8ºregulator-state-mem¼LDO_REG8+?Qw@i2Z  ­vcc1v8_dvpºregulator-state-mem¼LDO_REG9+?Q*¹€i*¹€ ­vcc2v8_dvpregulator-state-mem¼BOOST+?QG·`iReÀ­boostº%regulator-state-mem¼OTG_SWITCH ­otg_switchregulator-state-mem¼charger &'>“àd† regulator@40 ,fcs,fan53555 @‹+?Q ß4i5°­vdd_cpuü¨$ºregulator-state-mem¼power-monitor@62,cellwise,cw2015 b ‡disabledserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart ýÕ ˜t ,baudclkapb_pclk³''ð(údefault¸Å ‡disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm ý× 0 pwmpclkð)údefaultχokayºÇpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm ý× 0 pwmpclkð*údefaultÏ ‡disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm ý×  0 pwmpclkð+údefaultÏ ‡disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm ý×0 0 pwmpclkð,údefaultÏ ‡disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfd ýÙpower-controller!,rockchip,rk3568-power-controllerÚ ºpower-domain@7 î-Úpower-domain@8 ÌÍ î./0Úpower-domain@9 ÚÛÜ î123Úpower-domain@10 ñòî456789Úpower-domain@11 íî:Úpower-domain@13 î;Úpower-domain@14  î<�=>Úpower-domain@15 î?@ABCÚgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost ýæ@$˜()' õjobmmugpugpubus2D<�‡okayEº¢video-codec@fdea0400,rockchip,rk3568-vpu ýê ˜‹õvdpuîï aclkhclkF<� iommu@fdea0800,rockchip,rk3568-iommu ýê@ ˜Š aclkifaceîï<� ºFrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ýë€ ˜Zóôõaclkhclksclk[&$% %coreaxiahb<� video-codec@fdee0000,rockchip,rk3568-vepu ýî ˜@ýþ aclkhclkG<� iommu@fdee0800,rockchip,rk3568-iommu ýî@ ˜?ýþ aclkiface<� ºGmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc þ@ ˜d ÁÂŽbiuciuciu-driveciu-sample1<ðÑ€[ë%reset‡okayJTerˆH“š  ðIJKúdefault®»LÇMethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a þ˜ õmacirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref[ì %stmmaceth“ÔNäõOP ‡disabledmdio,snps,dwmac-mdio stmmac-axi-config$.>ºNrx-queues-configNºOqueue0tx-queues-configdºPqueue0vop@fe040000  þ0þ@zvopgamma-lut ˜”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2Q<� “‡okay,rockchip,rk3566-vopWßà|ports ºport@0  endpoint@2 „Rº_port@1  endpoint@4 „SºUport@2  iommu@fe043e00,rockchip,rk3568-iommu  þ>þ? ˜”ÝÞ aclkiface<� ‡okayºQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi þ ˜Dpclkè dphyT<� %apb[“‡okay ports port@0 endpoint„UºSport@1 endpoint„Vº[panel@0(,anbernic,rg353p-panelnewvision,nv3051d ”WúdefaultðX žYªZportendpoint„[ºVdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi þ ˜Epclké dphy\<� %apb[“ ‡disabledports port@0 port@1 hdmi@fe0a0000,rockchip,rk3568-dw-hdmi þ  ˜-(æç“(Úiahbisfrcecrefúdefaultð]<� ¸“ ‡okayµ^ºports port@0 endpoint„_ºRport@1 endpoint„`ºÄqos@fe128000,rockchip,rk3568-qossyscon þ€ º-qos@fe138080,rockchip,rk3568-qossyscon þ€€ º<�qos@fe138100,rockchip,rk3568-qossyscon þ º=qos@fe138180,rockchip,rk3568-qossyscon þ€ º>qos@fe148000,rockchip,rk3568-qossyscon þ€ º.qos@fe148080,rockchip,rk3568-qossyscon þ€€ º/qos@fe148100,rockchip,rk3568-qossyscon þ º0qos@fe150000,rockchip,rk3568-qossyscon þ º:qos@fe158000,rockchip,rk3568-qossyscon þ€ º4qos@fe158100,rockchip,rk3568-qossyscon þ º5qos@fe158180,rockchip,rk3568-qossyscon þ€ º6qos@fe158200,rockchip,rk3568-qossyscon þ‚ º7qos@fe158280,rockchip,rk3568-qossyscon þ‚€ º8qos@fe158300,rockchip,rk3568-qossyscon þƒ º9qos@fe180000,rockchip,rk3568-qossyscon þ qos@fe190000,rockchip,rk3568-qossyscon þ º?qos@fe190280,rockchip,rk3568-qossyscon þ€ º@qos@fe190300,rockchip,rk3568-qossyscon þ ºAqos@fe190380,rockchip,rk3568-qossyscon þ€ ºBqos@fe190400,rockchip,rk3568-qossyscon þ ºCqos@fe198000,rockchip,rk3568-qossyscon þ€ º;qos@fe1a8000,rockchip,rk3568-qossyscon þ€ º1qos@fe1a8080,rockchip,rk3568-qossyscon þ€€ º2qos@fe1a8100,rockchip,rk3568-qossyscon þ º3dfi@fe230000,rockchip,rk3568-dfi þ# ˜ Áapcie@fe260000,rockchip,rk3568-pcie0 À@þ&ôzdbiapbconfig<�˜KJIHGõsyspmcmsglegacyerrÎ(‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxþpci¥Ø`ëbbbbù   ( 7 ?  pcie-phy<�Tôôô ô à@@[¡%pipe  ‡disabledlegacy-interrupt-controller¥ ˜Hºbmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc þ+@ ˜b °±Š‹biuciuciu-driveciu-sample1<ðÑ€[Ô%reset‡okayJT I! Rðcdefúdefault ]»Çmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc þ,@ ˜c ²³Œbiuciuciu-driveciu-sample1<ðÑ€[Ö%reset‡okayJT Ig  Rðhijkúdefault ]»Çspi@fe300000 ,rockchip,sfc þ0@ ˜exvclk_sfchclk_sfcðlúdefault ‡disabledmmc@fe310000,rockchip,rk3568-dwcmshc þ1 ˜W{}g ëÂn6(|zy{}corebusaxiblocktimer‡okayðmnopqúdefaultJ k »Çi2s@fe400000,rockchip,rk3568-i2s-tdm þ@ ˜4W=AgFÏqFÏq?C9mclk_txmclk_rxhclk³r ztx[PQ %tx-mrx-m“ ‡okayº i2s@fe410000,rockchip,rk3568-i2s-tdm þA ˜5WEIgFÏqFÏqGK:mclk_txmclk_rxhclk³rr zrxtx[RS %tx-mrx-m“údefaultðstuv ‡okay „ºÑi2s@fe420000,rockchip,rk3568-i2s-tdm þB ˜6WMgFÏqOO;mclk_txmclk_rxhclk³rr ztxrx[T%tx-m“údefaultðwxyz  ‡disabledi2s@fe430000,rockchip,rk3568-i2s-tdm þC ˜7SW<�mclk_txmclk_rxhclk³rr ztxrx[UV %tx-mrx-m“  ‡disabledpdm@fe440000,rockchip,rk3568-pdm þD ˜LZYpdm_clkpdm_hclk³r  zrxð{|}~€údefault[X%pdm-m  ‡disabledspdif@fe460000,rockchip,rk3568-spdif þF ˜f mclkhclk_\³r ztxúdefaultð  ‡disableddma-controller@fe530000,arm,pl330arm,primecell þS@˜  Ÿ  apb_pclk ¶º'dma-controller@fe550000,arm,pl330arm,primecell þU@˜ Ÿ  apb_pclk ¶ºri2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þZ ˜/HG i2cpclkð‚údefault  ‡disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þ[ ˜0JI i2cpclkðƒúdefault ‡okay Ádefaulttouch@1a,hynitron,cst340 Y˜ ð„údefault žY Ѐ ãài2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þ\ ˜1LK i2cpclkð…údefault  ‡disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þ] ˜2NM i2cpclkð†údefault  ‡disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þ^ ˜3PO i2cpclkð‡údefault ‡okayº^watchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt þ` ˜• tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spi þa ˜gRQspiclkapb_pclk³'' ztxrxúdefault ðˆ‰Š  ‡disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spi þb ˜hTSspiclkapb_pclk³'' ztxrxúdefault ð‹Œ  ‡disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spi þc ˜iVUspiclkapb_pclk³'' ztxrxúdefault ðŽ  ‡disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spi þd ˜jXWspiclkapb_pclk³'' ztxrxúdefault ð‘’“  ‡disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uart þe ˜ubaudclkapb_pclk³'' 𔕖údefault¸Å‡okay öbluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt Y Y %Yserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uart þf ˜v# baudclkapb_pclk³''ð—údefault¸Å‡okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uart þg ˜w'$baudclkapb_pclk³''ð˜údefault¸Å ‡disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uart þh ˜x+(baudclkapb_pclk³'' ð™údefault¸Å ‡disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uart þi ˜y/,baudclkapb_pclk³' ' ðšúdefault¸Å ‡disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uart þj ˜z30baudclkapb_pclk³' ' ð›údefault¸Å ‡disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uart þk ˜{74baudclkapb_pclk³''ðœúdefault¸Å ‡disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uart þl ˜|;8baudclkapb_pclk³''ðúdefault¸Å ‡disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uart þm ˜}?<�baudclkapb_pclk³''ðžúdefault¸Å ‡disabledthermal-zonescpu-thermal 5d Kè YŸtripscpu_alert0 ip uÐ?passiveº cpu_alert1 i$ø uÐ?passivecpu_crit is uÐ ?criticalcooling-mapsmap0 € 0 … ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal 5 Kè YŸtripsgpu-threshold ip uÐ?passivegpu-target i$ø uÐ?passiveº¡gpu-crit is uÐ ?criticalcooling-mapsmap0 €¡ …¢ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadc þq ˜sWgf@ ®`tsadcapb_pclk[‚ד ”súdefaultsleep𣠫¤ µ‡okay Ë âºŸsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradc þr ˜]saradcapb_pclk[€ %saradc-apb ý‡okay ºÀpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm þnZY pwmpclkð¥údefaultχokayºÐpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm þnZY pwmpclkð¦údefaultχokayºÌpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm þn ZY pwmpclkð§údefaultχokayºÅpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm þn0ZY pwmpclkð¨údefaultχokayºÆpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm þo]\ pwmpclkð©údefaultÏ ‡disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm þo]\ pwmpclkðªúdefaultÏ ‡disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm þo ]\ pwmpclkð«údefaultÏ ‡disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm þo0]\ pwmpclkð¬údefaultÏ ‡disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwm þp`_ pwmpclkð­údefaultÏ ‡disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwm þp`_ pwmpclkð®údefaultÏ ‡disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwm þp `_ pwmpclkð¯údefaultÏ ‡disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwm þp0`_ pwmpclkð°údefaultÏ ‡disabledphy@fe830000,rockchip,rk3568-naneng-combphy þƒ"} refapbpipeW"gõá[Ç ± -² C‡okayºphy@fe840000,rockchip,rk3568-naneng-combphy þ„%~ refapbpipeW%gõá[É ± -³ C ‡disabledºphy@fe870000,rockchip,rk3568-csi-dphy þ‡ypclk C[º%apb“ ‡disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy þ… refpclkz C<� %apb[»‡okayºTmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy þ† refpclk{ C<� %apb[¼ ‡disabledº\usb2phy@fe8a0000,rockchip,rk3568-usb2phy þŠphyclkÝclk_usbphy0_480m ˜‡ N´0‡okayºhost-port C ‡disabledotg-port C‡okayºusb2phy@fe8b0000,rockchip,rk3568-usb2phy þ‹phyclkÝclk_usbphy1_480m ˜ˆ Nµ0‡okayhost-port C‡okayºotg-port C ‡disabledºpinctrl,rockchip,rk3568-pinctrl“Áa º¶gpio@fdd60000,rockchip,gpio-bank ýÖ ˜!.  ^ n¶  z¥º!gpio@fe740000,rockchip,gpio-bank þt ˜"cd ^ n¶  z¥gpio@fe750000,rockchip,gpio-bank þu ˜#ef ^ n¶@  z¥ºggpio@fe760000,rockchip,gpio-bank þv ˜$gh ^ n¶`  z¥ºÂgpio@fe770000,rockchip,gpio-bank þw ˜%ij ^ n¶€  z¥ºYpcfg-pull-up †º¹pcfg-pull-none “º·pcfg-pull-none-drv-level-1 “  º»pcfg-pull-none-drv-level-2 “  ººpcfg-pull-none-drv-level-3 “  º¾pcfg-pull-up-drv-level-1 †  º½pcfg-pull-up-drv-level-2 †  º¸pcfg-pull-none-smt “ ¯º¼pcfg-output-low ĺ¿acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 Ï·ºcpuebcedpdpemmcemmc-rstnout Ï·ºqemmc-bus8€ Ï ¸ ¸¸¸¸¸¸¸ºmemmc-clk ϸºnemmc-cmd ϸºoemmc-datastrobe Ï·ºpeth0eth1flashfspifspi-pins` Ï······ºlgmac0gmac1gpuhdmitxhdmitxm0-cec Ï·º]i2c0i2c0-xfer Ï ¼ ¼º i2c1i2c1-xfer Ï ¼ ¼º‚i2c2i2c2m1-xfer Ï ¼ ¼ºƒi2c3i2c3m0-xfer ϼ¼º…i2c4i2c4m0-xfer Ï ¼ ¼º†i2c5i2c5m1-xfer ϼ¼º‡i2s1i2s1m0-lrcktx Ï·ºti2s1m0-mclk Ï·º"i2s1m0-sclktx Ï·ºsi2s1m0-sdi0 Ï ·ºui2s1m0-sdo0 Ï·ºvi2s2i2s2m0-lrcktx Ï·ºxi2s2m0-sclktx Ï·ºwi2s2m0-sdi Ï·ºyi2s2m0-sdo Ï·ºzi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Ï·º{pdmm0-clk1 Ï·º|pdmm0-sdi0 Ï ·º}pdmm0-sdi1 Ï ·º~pdmm0-sdi2 Ï ·ºpdmm0-sdi3 Ï·º€pmicpmic-int-l Ϲº#pmupwm0pwm0m1-pins Ï·º)pwm1pwm1m0-pins Ï·º*pwm2pwm2m0-pins Ï·º+pwm3pwm3-pins Ï·º,pwm4pwm4-pins Ï·º¥pwm5pwm5-pins Ï·º¦pwm6pwm6-pins Ï·º§pwm7pwm7-pins Ï·º¨pwm8pwm8m0-pins Ï ·º©pwm9pwm9m0-pins Ï ·ºªpwm10pwm10m0-pins Ï ·º«pwm11pwm11m0-pins Ï·º¬pwm12pwm12m0-pins Ï·º­pwm13pwm13m0-pins Ï·º®pwm14pwm14m0-pins Ï·º¯pwm15pwm15m0-pins Ï·º°refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ϸ¸¸¸ºcsdmmc0-clk ϸºdsdmmc0-cmd ϸºesdmmc0-det Ϲºfsdmmc1sdmmc1-bus4@ ϸ¸¸¸ºhsdmmc1-clk ϸºjsdmmc1-cmd ϸºisdmmc1-det Ï ¹ºksdmmc2sdmmc2m0-bus4@ ϸ¸¸¸ºIsdmmc2m0-clk ϸºKsdmmc2m0-cmd ϸºJspdifspdifm0-tx Ï·ºspi0spi0m0-pins0 Ï ···ºŠspi0m0-cs0 Ï·ºˆspi0m0-cs1 Ï·º‰spi1spi1m0-pins0 Ï ···ºspi1m0-cs0 Ï·º‹spi1m0-cs1 Ï·ºŒspi2spi2m0-pins0 Ï···ºspi2m0-cs0 Ï·ºŽspi2m0-cs1 Ï·ºspi3spi3m0-pins0 Ï ·· ·º“spi3m0-cs0 Ï·º‘spi3m0-cs1 Ï·º’tsadctsadc-shutorg Ï·º£tsadc-pin Ï·º¤uart0uart0-xfer Ϲ¹º(uart1uart1m1-xfer Ϲ¹º”uart1m1-ctsn Ï·º•uart1m1-rtsn Ï·º–uart2uart2m0-xfer Ϲ¹º—uart3uart3m0-xfer Ϲ¹º˜uart4uart4m0-xfer Ϲ¹º™uart5uart5m0-xfer Ϲ¹ºšuart6uart6m0-xfer Ϲ¹º›uart7uart7m0-xfer Ϲ¹ºœuart8uart8m0-xfer Ϲ¹ºuart9uart9m0-xfer Ϲ¹ºžvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-btnsbtn-pins-ctrl Ϲ¹¹¹¹¹ ¹ ¹ ¹ ¹ ¹¹¹¹¹¹ºÁbtn-pins-vol Ϲ¹ºÃjoy-muxjoy-mux-en Ï ¿ºÎsdio-pwrseqwifi-enable-h Ï·ºÉvcc3v3-lcdvcc-lcd-h Ï·ºÊvcc-wifivcc-wifi-h Ï·ºËgpio-lcdlcd-rst Ï·ºXtouchtouch-rst Ϲº„chosen Ýserial2:1500000n8adc-keys ,adc-keys éÀ õbuttons w@ <�button-mode .MODE 4<� ?Ögpio-keys-control ,gpio-keysðÁúdefaultbutton-b ¤Â .SOUTH 40button-down ¤Â .DPAD-DOWN 4!button-l1 ¤Â  .TL 46button-l2 ¤Â  .TL2 48button-select ¤Â .SELECT 4:button-start ¤Â  .START 4;button-up ¤Â .DPAD-UP 4 button-x ¤Â .NORTH 43button-a ¤Â .EAST 41button-left ¤Â .DPAD-LEFT 4"button-right ¤Â .DPAD-RIGHT 4#button-thumbl ¤Â .THUMBL 4=button-thumbr ¤Â .THUMBR 4>button-y ¤Â .WEST 44button-r1 ¤Â  .TR 47button-r2 ¤Â  .TR2 49gpio-keys-vol ,gpio-keys YðÃúdefaultbutton-vol-down ¤Â .VOLUMEDOWN 4rbutton-vol-up ¤Â .VOLUMEUP 4shdmi-con,hdmi-connectorµ^?cportendpoint„ĺ`pwm-leds ,pwm-ledsled-0 d jon xpower ÿ Åa¨led-1 d xcharging ÿ Æa¨led-2 d joff xstatus ÿ Ça¨sdio-pwrseq,mmc-pwrseq-simpleÈ ext_clockðÉúdefault •È žYºHregulator-vcc3v3-lcd0,regulator-fixed ¬! ±ðÊúdefault?Q2Z i2Z ­vcc3v3_lcd0_n¨ºZregulator-state-mem¼regulator-vcc-sys,regulator-fixed+?Q9ûÀi9ûÀ­vcc_sysº$regulator-vcc-wifi,regulator-fixed ± ¬!ðËúdefault+?Q2Z i2Z  ­vcc_wifiºLpwm-vibrator ,pwm-vibrator Äenable Ì;šÊadc-joystick ,adc-joystick éÍÍÍÍðÎúdefault <� axis@0  Î  ×  àÿ 4axis@1  Î  ×  àÿ 4axis@2  Î  ×  àÿ 4axis@3  Î  ×  àÿ 4adc-mux,io-channel-mux ìleft_xright_xleft_yright_y ý éÀ õparent êÏ ÷dºÍbacklight,pwm-backlight $ Ða¨ºWmux-controller ,gpio-mux !! ºÏbattery,simple-battery 00˜ R“à o„€ ”@@ ºÉ á?¨à þ3á@¨0?¨àd=Ûð_<Ê€Z;çðU;ÐP:aPK9¹XF9(ÐA8«Ð<�82¸77±Ð27[à-7`(6î€#6»¸6}8635Ɉ5H  4”ð3á@º&sound,simple-audio-card =rk817_intTi2s EYmCcMicrophoneMic JackHeadphoneHeadphonesSpeakerInternal SpeakersE}MICLMic JackHeadphonesHPOLHeadphonesHPORInternal SpeakersSPKOsimple-audio-card,codecŽÈsimple-audio-card,cpuŽÑ interrupt-parent#address-cells#size-cellscompatiblechassis-typemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2mmc3device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr50vmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointbacklightreset-gpiosvdd-supplyddc-i2c-busrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpsd-uhs-sdr104mmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellspintctrl-namestouchscreen-size-xtouchscreen-size-yuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltautorepeatcolordefault-statefunctionmax-brightnesspwmspost-power-on-delay-msgpioenable-active-highpwm-namesabs-flatabs-fuzzabs-rangemux-controlssettle-time-uspower-supplymux-gpios#mux-control-cellscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0simple-audio-card,hp-det-gpiosimple-audio-card,widgetssimple-audio-card,routing