Ð þí&8\(Ê$hisilicon,hip05-d02 +&7Hisilicon Hip05 D02 Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cluster2core0D core1D core2D core3D cluster3core0Dcore1Dcore2Dcore3Dcpu@20000Hcpuarm,cortex-a57TXpscifwcpu@20001Hcpuarm,cortex-a57TXpscifwcpu@20002Hcpuarm,cortex-a57TXpscifwcpu@20003Hcpuarm,cortex-a57TXpscifwcpu@20100Hcpuarm,cortex-a57TXpscifwcpu@20101Hcpuarm,cortex-a57TXpscifwcpu@20102Hcpuarm,cortex-a57TXpscifwcpu@20103Hcpuarm,cortex-a57TXpscifw cpu@20200Hcpuarm,cortex-a57TXpscifw cpu@20201Hcpuarm,cortex-a57TXpscifw cpu@20202Hcpuarm,cortex-a57TXpscifw cpu@20203Hcpuarm,cortex-a57TXpscifw cpu@20300Hcpuarm,cortex-a57TXpscifwcpu@20301Hcpuarm,cortex-a57TXpscifwcpu@20302Hcpuarm,cortex-a57TXpscifwcpu@20303Hcpuarm,cortex-a57TXpscifwl2-cache0cache‹wl2-cache1cache‹wl2-cache2cache‹wl2-cache3cache‹winterrupt-controller@8d000000 arm,gic-v3™+ª±ÆÝPT0þþþ ò wmsi-controller@8c000000arm,gic-v3-itsý TŒmsi-controller@a3000000arm,gic-v3-itsý T£msi-controller@b7000000arm,gic-v3-itsý T·msi-controller@c6000000arm,gic-v3-itsý TÆrefclk200mhz fixed-clock$ ëÂwtimerarm,armv8-timer0ò   pmuarm,cortex-a57-pmu òsoc simple-bus+ªserial@80300000snps,dw-apb-uartT€0 ò=4;baudclkapb_pclkGQ^okayserial@80310000snps,dw-apb-uartT€1 ò>4;baudclkapb_pclkGQ ^disabledlocal-bus@80380000#hisilicon,hisi-localbussimple-busT€8^okay+(ª˜nor-flash@0+numonyx,js28f00acfi-flash Tepartition@0pBIOST0partition@300000pLinuxT0 partition@1000000pRootfsTcpld@100000000hisilicon,hip05-cpld Tgpio@802e0000+snps,dw-apb-gpioT€.^okaygpio-controller@0snps,dw-apb-gpio-portv†’ T±™ ò8wgpio@802f0000+snps,dw-apb-gpioT€/ ^disabledgpio-controller@0snps,dw-apb-gpio-portv†’ T±™ ò9memory@0HmemoryT€aliases™/soc/serial@80300000chosen¡serial0:115200n8gpio-keys gpio-keyspwr-button pPower Button “­t¸ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachephandlecache-levelcache-unified#interrupt-cellsrangesinterrupt-controller#redistributor-regionsredistributor-strideinterruptsmsi-controller#msi-cells#clock-cellsclock-frequencyclocksclock-namesreg-shiftreg-io-widthstatusbank-widthlabelgpio-controller#gpio-cellsngpiosserial0stdout-pathlinux,codedebounce-interval