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þíÙ%8Í(ÌÐ &,firefly,rk3566-roc-pcrockchip,rk35667Firefly Station M2aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe2b0000ì/mmc@fe310000ñ/mmc@fe2c0000cpus cpu@0öcpu,arm,cortex-a55
psci*>€K@]€j€w@‰€–§²
cpu@100öcpu,arm,cortex-a55
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psci
,arm,psci-1.0#smctimer,arm,armv8-timer0
®xin24m,fixed-clockÅn6Õxin24m(²xin32k,fixed-clockÅ€Õxin32kèòdefault(sram@10f000
,mmio-sramð ðsram@0,arm,scmi-shmem²sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@›œsatapmaliverxoob_ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢satapmaliverxoob` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@©¦§¥ref_clksuspend_clkbus_clkBotg
Jutmi_wide4S”Zokay usb2-physzhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ª©ª¨ref_clksuspend_clkbus_clkBhostusb2-phyusb3-phy
Jutmi_wide4S•Zokayinterrupt-controller@fd400000,arm,gic-v3 ý@ýF ˆ®ýA¸(òusb@fd800000
,generic-ehciý€‚½¾¼usbokayusb@fd840000
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,generic-ehciýˆ…¿À¼usb disabledusb@fd8c0000
,generic-ohciýŒ†¿À¼usb disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý²]io-domains&,rockchip,rk3568-pmu-io-voltage-domainokayÒàîü
&4Bsyscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsyscon²±syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƲsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȲ²syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɲ³syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€²´syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€²·clock-controller@fdd00000,rockchip,rk3568-pmucruýÐ(P²clock-controller@fdd20000,rockchip,rk3568-cruýÒxin24m(P]m€G†Œë‚™²i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ.- i2cpclkè òdefault okayregulator@1c,tcs,tcs4525¦Ãvdd_cpuÒ5êŒ0ü+=!²regulator-state-memHpmic@20,rockchip,rk809 "Õrk808-clkout1rk808-clkout2]H‚–mclkHòdefaultè#$a‚(¡%%¹%Å%Ñ%Ý%é%õ%%²’codec
regulatorsDCDC_REG1Ãvdd_log+Ò¡ ê™pqregulator-state-mem*B
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Ãvcc3v3_sd+²fserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕt,baudclkapb_pclku&&è'òdefaultz‡okaypwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×
0 pwmpclkè(òdefault‘ disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×
0 pwmpclkè)òdefault‘ disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×
0 pwmpclkè*òdefault‘ disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0
0 pwmpclkè+òdefault‘ disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerœ ²power-domain@7°,œpower-domain@8ÌÍ°-./œpower-domain@9 ÚÛÜ°012œpower-domain@10
ñò°345678œpower-domain@11í°9œpower-domain@13
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*C4okayÇD²¢video-codec@fdea0400,rockchip,rk3568-vpuýê‹·vdpuîï
aclkhclkÓE4iommu@fdea0800,rockchip,rk3568-iommuýê@Šaclkifaceîï4Ú²Erga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ZóôõaclkhclksclkS&$%
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Ú²Fmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@d ÁÂŽbiuciuciu-driveciu-sampleóþðÑ€Sëçreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ ·macirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refSì
çstmmaceth™G-H@ISokay]‰‡†‚‡†J\inputirgmiiròdefaultèKLMNOP}"£N † ¸OÁ$ÊQmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22²Qstmmac-axi-configÕßï²Grx-queues-configÿ²Hqueue0tx-queues-config²Iqueue0vop@fe040000 þ0þ@+vopgamma-lut”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2ÓR4 ™okay,rockchip,rk3566-vop]ßà‚ports ²port@0 endpoint@25S²[port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ?”ÝÞaclkifaceÚ4 okay²Rdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþDpclkèdphyT4 çapbS™ disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþEpclkédphyU4 çapbS™ disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ
-(æç“(ÚiahbisfrcecrefòdefaultèVWX4 z™okayEYUZ²ports port@0endpoint5[²Sport@1endpoint5\²Âqos@fe128000,rockchip,rk3568-qossysconþ€ ²,qos@fe138080,rockchip,rk3568-qossysconþ€€ ²;qos@fe138100,rockchip,rk3568-qossysconþ ²<�qos@fe138180,rockchip,rk3568-qossysconþ€ ²=qos@fe148000,rockchip,rk3568-qossysconþ€ ²-qos@fe148080,rockchip,rk3568-qossysconþ€€ ².qos@fe148100,rockchip,rk3568-qossysconþ ²/qos@fe150000,rockchip,rk3568-qossysconþ ²9qos@fe158000,rockchip,rk3568-qossysconþ€ ²3qos@fe158100,rockchip,rk3568-qossysconþ ²4qos@fe158180,rockchip,rk3568-qossysconþ€ ²5qos@fe158200,rockchip,rk3568-qossysconþ‚ ²6qos@fe158280,rockchip,rk3568-qossysconþ‚€ ²7qos@fe158300,rockchip,rk3568-qossysconþƒ ²8qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ²>qos@fe190280,rockchip,rk3568-qossysconþ€ ²?qos@fe190300,rockchip,rk3568-qossysconþ ²@qos@fe190380,rockchip,rk3568-qossysconþ€ ²Aqos@fe190400,rockchip,rk3568-qossysconþ ²Bqos@fe198000,rockchip,rk3568-qossysconþ€ ²:qos@fe1a8000,rockchip,rk3568-qossysconþ€ ²0qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ²1qos@fe1a8100,rockchip,rk3568-qossysconþ ²2dfi@fe230000,rockchip,rk3568-dfiþ#e]pcie@fe260000,rockchip,rk3568-pcie0À@þ&ô+dbiapbconfig<�KJIHG·syspmcmsglegacyerrr(‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxöpci|`^^^^®½ÌÛã pcie-phy4Tôôô ô à@@S¡çpipe okayòdefaultè_í`
ùalegacy-interrupt-controllerˆH²^mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@b °±Š‹biuciuciu-driveciu-sampleóþðÑ€SÔçresetokay $" -òdefaultèbcde 8 Ff Rmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@c ²³Œbiuciuciu-driveciu-sampleóþðÑ€SÖçresetokay _ l ‚g F% Rhòdefaultèijkspi@fe300000
,rockchip,sfcþ0@exvclk_sfchclk_sfcèlòdefault disabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1]{}mëÂn6(|zy{}corebusaxiblocktimerokay œ F Ri2s@fe400000,rockchip,rk3568-i2s-tdmþ@4]=AmFÏqFÏq?C9mclk_txmclk_rxhclkum ªtxSPQ
çtx-mrx-m™okay² i2s@fe410000,rockchip,rk3568-i2s-tdmþA5]EImFÏqFÏqGK:mclk_txmclk_rxhclkumm ªrxtxSRS
çtx-mrx-m™òdefaultènopqrsokay ´²Äi2s@fe420000,rockchip,rk3568-i2s-tdmþB6]MmFÏqOO;mclk_txmclk_rxhclkumm ªtxrxSTçtx-m™òdefaultètuvw disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC7SW<�mclk_txmclk_rxhclkumm ªtxrxSUV
çtx-mrx-m™ disabledpdm@fe440000,rockchip,rk3568-pdmþDLZYpdm_clkpdm_hclkum ªrxèxyz{|}òdefaultSXçpdm-m disabledspdif@fe460000,rockchip,rk3568-spdifþFf
mclkhclk_\um ªtxòdefaultè~ disableddma-controller@fe530000,arm,pl330arm,primecellþS@
Ï
apb_pclk æ²&dma-controller@fe550000,arm,pl330arm,primecellþU@ Ï
apb_pclk æ²mi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ/HG i2cpclkèòdefault okayi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[0JI i2cpclkè€òdefault okayi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\1LK i2cpclkèòdefault okayi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ]2NM i2cpclkè‚òdefault disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^3PO i2cpclkèƒòdefault disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ`•
tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþagRQspiclkapb_pclku&& ªtxrxòdefaultè„…† disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþbhTSspiclkapb_pclku&& ªtxrxòdefault臈‰ disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþciVUspiclkapb_pclku&& ªtxrxòdefault芋Œ disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþdjXWspiclkapb_pclku&& ªtxrxòdefaultèŽ disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþeubaudclkapb_pclku&&è‘òdefaultz‡okay ñbluetooth,brcm,bcm43438-bt’lpo
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&èšòdefaultz‡ disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþjz30baudclkapb_pclku&&
è›òdefaultz‡ disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk{74baudclkapb_pclku&&èœòdefaultz‡ disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl|;8baudclkapb_pclku&&èòdefaultz‡ disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm}?<�baudclkapb_pclku&&èžòdefaultz‡ disabledthermal-zonescpu-thermal
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å disabledpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¥òdefault‘ disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¦òdefault‘ disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY pwmpclkè§òdefault‘ disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY pwmpclkè¨òdefault‘ disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè©òdefault‘ disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkèªòdefault‘ disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ pwmpclkè«òdefault‘ disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ pwmpclkè¬òdefault‘ disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkèòdefault‘ disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè®òdefault‘ disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ pwmpclkè¯òdefault‘ disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ pwmpclkè°òdefault‘ disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"}
refapbpipe]"mõáSÇ
÷± ²okay²phy@fe840000,rockchip,rk3568-naneng-combphyþ„%~
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÷± ³okay²phy@fe870000,rockchip,rk3568-csi-dphyþ‡ypclkSºçapb™ disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… refpclkz4 çapbS» disabled²Tmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† refpclk{4 çapbS¼ disabled²Uusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠphyclkÕclk_usbphy0_480m‡*´(okay²host-portokayrµ²otg-portokayr¶²usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹phyclkÕclk_usbphy1_480mˆ*·(okayhost-port disabled²otg-portokayrµ²pinctrl,rockchip,rk3568-pinctrl™e] ²¸gpio@fdd60000,rockchip,gpio-bankýÖ!.:J¸ Vˆ²"gpio@fe740000,rockchip,gpio-bankþt"cd:J¸ Vˆ²`gpio@fe750000,rockchip,gpio-bankþu#ef:J¸@ Vˆ²“gpio@fe760000,rockchip,gpio-bankþv$gh:J¸` Vˆgpio@fe770000,rockchip,gpio-bankþw%ij:J¸€ Vˆpcfg-pull-upb²»pcfg-pull-downo²Ápcfg-pull-none~²¹pcfg-pull-none-drv-level-1~‹²½pcfg-pull-none-drv-level-2~‹²¼pcfg-pull-none-drv-level-3~‹²Àpcfg-pull-up-drv-level-1b‹²¿pcfg-pull-up-drv-level-2b‹²ºpcfg-pull-none-smt~š²¾acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0¯¹²cpuebcedpdpemmceth0eth1flashfspifspi-pins`¯¹¹¹¹¹¹²lgmac0gmac1gmac1m0-miim ¯¹¹²Kgmac1m0-clkinout¯¹²Ogmac1m0-rx-bus20¯ ¹
¹¹²Mgmac1m0-tx-bus20¯
¼¼¹²Lgmac1m0-rgmii-clk ¯¹½²Ngmac1m0-rgmii-bus@¯¹¹¼¼²Pgpuhdmitxhdmitxm0-cec¯¹²Xhdmitx-scl¯¹²Vhdmitx-sda¯¹²Wi2c0i2c0-xfer ¯ ¾
¾² i2c1i2c1-xfer ¯¾¾²i2c2i2c2m0-xfer ¯
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¾²‚i2c5i2c5m0-xfer ¯¾¾²ƒi2s1i2s1m0-lrckrx¯¹²qi2s1m0-lrcktx¯¹²pi2s1m0-mclk¯¹²$i2s1m0-sclkrx¯¹²oi2s1m0-sclktx¯¹²ni2s1m0-sdi0¯¹²ri2s1m0-sdo0¯¹²si2s2i2s2m0-lrcktx¯¹²ui2s2m0-sclktx¯¹²ti2s2m0-sdi¯¹²vi2s2m0-sdo¯¹²wi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk¯¹²xpdmm0-clk1¯¹²ypdmm0-sdi0¯¹²zpdmm0-sdi1¯
¹²{pdmm0-sdi2¯ ¹²|pdmm0-sdi3¯¹²}pmicpmic_int¯»²#pmupwm0pwm0m0-pins¯¹²(pwm1pwm1m0-pins¯¹²)pwm2pwm2m0-pins¯¹²*pwm3pwm3-pins¯¹²+pwm4pwm4-pins¯¹²¥pwm5pwm5-pins¯¹²¦pwm6pwm6-pins¯¹²§pwm7pwm7-pins¯¹²¨pwm8pwm8m0-pins¯ ¹²©pwm9pwm9m0-pins¯
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ˆ"òdefaultèÉÒLK@êLK@=!²¶ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-source#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyrockchip,mic-in-differentialregulator-on-in-suspendregulator-suspend-microvoltregulator-initial-modedmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqmmc-hs200-1_8vnon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cells#io-channel-cellsrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabeldefault-statelinux,default-triggerretain-state-suspendedenable-active-high