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opp-871000000Î3êgÀÕ Ô Æ opp-923000000Î7ÜÀÕ5²Æ opp-962000000Î9Vô€Õf†Æ opp-1027000000Î=6ÆÀÕà˜Æopp-1092000000ÎA™ÕB@Æopp-1144000000ÎD0Õ£èÆopp-1196000000ÎGIƒÕÆccimediatek,mt8183-cciñøcciintermediateÆ"cpus+cpu-mapcluster0core0$core1$core2$core3$cluster1core0$core1$core2$core3$cpu@0(cpuarm,cortex-a5348psciFåYñøcpuintermediate iTƒ€@¢¯€¼@΀Û!ìû"Æcpu@1(cpuarm,cortex-a5348psciFåYñøcpuintermediate iTƒ€@¢¯€¼@΀Û!ìû"Æcpu@2(cpuarm,cortex-a5348psciFåYñøcpuintermediate iTƒ€@¢¯€¼@΀Û!ìû"Æcpu@3(cpuarm,cortex-a5348psciFåYñøcpuintermediate iTƒ€@¢¯€¼@΀Û!ìû"Æcpu@100(cpuarm,cortex-a7348psciFY#ñøcpuintermediate$iÓƒ@¢¯¼@ÎÛ%ìû"&Æcpu@101(cpuarm,cortex-a7348psciFY#ñøcpuintermediate$iÓƒ@¢¯¼@ÎÛ%ìû"&Æcpu@102(cpuarm,cortex-a7348psciFY#ñøcpuintermediate$iÓƒ@¢¯¼@ÎÛ%ìû"&Æcpu@103(cpuarm,cortex-a7348psciFY#ñøcpuintermediate$iÓƒ@¢¯¼@ÎÛ%ìû"&Æidle-statespscicpu-sleeparm,idle-state&=ÈNÈ^ Æcluster-sleep-0arm,idle-state&=úN^èÆcluster-sleep-1arm,idle-state&=úN^Æ#l2-cache0cacheo…’@¤{Æ!l2-cache1cacheo…’@¤{Æ%opp-table-0operating-points-v2»Æ|opp-300000000Îá£Õ ‰hopp-320000000ÎÐÕ ¡Òopp-340000000ÎCýÕ º<�opp-360000000Îu*Õ Ò¦opp-380000000ΦWÕ ëopp-400000000ÎׄÕ zopp-420000000Î±Õ äopp-460000000Îk Õ L¸opp-500000000ÎÍeÕ }Œopp-540000000Î /¿Õ ®`opp-580000000Î"’Õ ß4opp-620000000Î$ôsÕ opp-653000000Î&ëý@Õ YFopp-698000000Î)š¢€Õ ºîopp-743000000Î,IGÀÕ –opp-800000000Î/¯Õ –¨pmu-a53arm,cortex-a53-pmu '‰(pmu-a73arm,cortex-a73-pmu '‰)psci arm,psci-1.0?smcfixed-factor-clock-13mfixed-factor-clock”ñ*¡«¶clk13mÆ;oscillator fixed-clock”ÉŒº€¶clk26mÆ*timerarm,armv8-timer '@‰   soc+ simple-busÙefuse@8000000%mediatek,mt8183-efusemediatek,efuse4+àokayinterrupt-controller@c000000 arm,gic-v3ç 'øP4   @ A B ‰  Æ'ppi-partitionsinterrupt-partition-0-Æ(interrupt-partition-1-Æ)syscon@c530000mediatek,mt8183-mcucfgsyscon4 S”Æinterrupt-controller@c530a80.mediatek,mt8183-sysirqmediatek,mt6577-sysirqøç '4 S €PÆcpu-debug@d410000&arm,coresight-cpu-debugarm,primecell4 Añ+. øapb_pclk$cpu-debug@d510000&arm,coresight-cpu-debugarm,primecell4 Qñ+. øapb_pclk$cpu-debug@d610000&arm,coresight-cpu-debugarm,primecell4 añ+. øapb_pclk$cpu-debug@d710000&arm,coresight-cpu-debugarm,primecell4 qñ+. øapb_pclk$cpu-debug@d810000&arm,coresight-cpu-debugarm,primecell4 ñ+. øapb_pclk$cpu-debug@d910000&arm,coresight-cpu-debugarm,primecell4 ‘ñ+. øapb_pclk$cpu-debug@da10000&arm,coresight-cpu-debugarm,primecell4 ¡ñ+. øapb_pclk$cpu-debug@db10000&arm,coresight-cpu-debugarm,primecell4 ±ñ+. øapb_pclk$syscon@10000000 mediatek,mt8183-topckgensyscon4”Æsyscon@10001000 mediatek,mt8183-infracfgsyscon4”6Æ+syscon@10003000mediatek,mt8183-pericfgsyscon40”Æmpinctrl@10005000mediatek,mt8183-pinctrl 4PòèçéÓÒÅó°DCiocfg0iocfg1iocfg2iocfg3iocfg4iocfg5iocfg6iocfg7iocfg8eintM]i,Àø ‰±çuSPI_AP_EC_CS_LSPI_AP_EC_MOSISPI_AP_EC_CLKI2S3_DOUSB_PD_INT_ODLIT6505_HPD_LI2S3_TDM_D3SOC_I2C6_1V8_SCLSOC_I2C6_1V8_SDADPI_D0DPI_D1DPI_D2DPI_D3DPI_D4DPI_D5DPI_D6DPI_D7DPI_D8DPI_D9DPI_D10DPI_D11DPI_HSYNCDPI_VSYNCDPI_DEDPI_CKAP_MSDC1_CLKAP_MSDC1_DAT3AP_MSDC1_CMDAP_MSDC1_DAT0AP_MSDC1_DAT2AP_MSDC1_DAT1OTG_ENDRVBUSDISP_PWMDSI_TELCM_RST_1V8AP_CTS_WIFI_RTSAP_RTS_WIFI_CTSSOC_I2C5_1V8_SCLSOC_I2C5_1V8_SDASOC_I2C3_1V8_SCLSOC_I2C3_1V8_SDASOC_I2C1_1V8_SDASOC_I2C0_1V8_SDASOC_I2C0_1V8_SCLSOC_I2C1_1V8_SCLAP_SPI_H1_MISOAP_SPI_H1_CS_LAP_SPI_H1_MOSIAP_SPI_H1_CLKI2S5_BCKI2S5_LRCKI2S5_DOBOOTBLOCK_EN_LMT8183_KPCOL0SPI_AP_EC_MISOUART_DBG_TX_AP_RXUART_AP_TX_DBG_RXI2S2_MCKI2S2_BCKCLK_5M_WCAMCLK_2M_UCAMI2S2_LRCKI2S2_DISOC_I2C2_1V8_SCLSOC_I2C2_1V8_SDASOC_I2C4_1V8_SCLSOC_I2C4_1V8_SDASCL8SDA8FCAM_PWDN_LI2S_PMICI2S_PMICI2S_PMICI2S_PMICI2S_PMICI2S_PMICI2S_PMICI2S_PMICAP_FLASH_WP_LEC_AP_INT_ODLIT6505_INT_ODLH1_INT_OD_LAP_SPI_FLASH_MISOAP_SPI_FLASH_CS_LAP_SPI_FLASH_MOSIAP_SPI_FLASH_CLKDA7219_IRQÆ,audiopinsÆ‹pins-busD…abefYZ[®ˆ‰Š‹ŒŽaudiotdmoutonÆŒpins-bus…©ª«¬­ Œaudiotdmoutoffƍpins-bus…©ª«¬­ ›¨Œbt-pinsÆFpins-bt-en…x·ec-ap-int-odlÆcpins1…—›Âh1-int-od-lÆXpins1…™›i2c0ÆIpins-bus…RSÏi2c1Æapins-bus…QTÏi2c2ÆUpins-bus…ghäi2c3Æ_pins-bus…23Ïi2c4ÆKpins-bus…ijäi2c5Æepins-bus…01Ïi2c6ÆHpins-bus…  ämmc0-pins-defaultÆqpins-cmd-dat$…{€}„~‚z›ŒÏpins-clk…|Œñ pins-rst……Œñmmc0-pins-uhsÆrpins-cmd-dat$…{€}„~‚z›ŒÏpins-clk…|Œñ pins-ds…ƒŒñ pins-rst……ŒÏmmc1-pins-defaultÆupins-cmd-dat… "!›Ï pins-clk…›ñ mmc1-pins-uhsÆvpins-cmd-dat… "!Œ›Ï pins-clk…Œñ ›panel-pins-defaultpanel-reset…-·Âpwm0-pin-defaultÆ^pins1…°Âpins2…+scpÆ:pins-scp-uart…npspi0ÆWpins-spi…UVWXäspi1Æ`pins-spi…¡¢£¤äspi2Æbpins-spi …äpins-spi-mi…^ñspi3Ædpins-spi…äspi4Æipins-spi…äspi5Æjpins-spi… äuart0-pins-defaultÆCpins-rx…_›Âpins-tx…`uart1-pins-defaultÆDpins-rx…y›Âpins-tx…spins-rts…/pins-cts….›uart1-pins-sleepÆEpins-rx…y›Âpins-tx…spins-rts…/pins-cts….›wifi-pins-pwrseqƏpins-wifi-enable…w·wifi-pins-wakeupƐpins-wifi-wakeup…q›pp1200-mipibrdg-enÆ‘pins1…6·pp1800-lcd-enÆ’pins1…$·pp3300-panel-pinsÆ“panel-3v3-enable…#·ppvarp-lcd-enpins1…B·ppvarn-lcd-enpins1…¦·anx7625-pinsÆLpins1…-I·pins2…›Âtouchscreen-pinsÆJtouch-int-odl…››Âtouch-rst-l…œtrackpad-pinsÆVtrackpad-int…›ävddio-mipibrdg-enÆ”pins1…%·volume-button-pinsÆ•voldn-btn-odl…›Âvolup-btn-odl…›Âda7219_pinsÆfpins1…¥›Âsyscon@10006000)mediatek,mt8183-scpsyssysconsimple-mfd4`power-controller!mediatek,mt8183-power-controller+Æ]power-domain@04ñ +/+7øaudioaudio1audio2power-domain@14(+power-domain@24ñømfg+:-power-domain@34+:.power-domain@44power-domain@54power-domain@64(+power-domain@74Xñ////////// 5ømmmm-0mm-1mm-2mm-3mm-4mm-5mm-6mm-7mm-8mm-9(+H0+power-domain@84@ñ11 11111.øcamcam-0cam-1cam-2cam-3cam-4cam-5cam-6(+H0power-domain@94 ñ"2 2øispisp-0isp-1(+H0power-domain@104 H0power-domain@114 H0power-domain@124 @ñ&#333333-øvpuvpu1vpu-0vpu-1vpu-2vpu-3vpu-4vpu-5(+H0+power-domain@134 ñ$øvpu2(+power-domain@144ñ%øvpu3(+watchdog@10007000mediatek,mt8183-wdt4p6Æosyscon@1000c000"mediatek,mt8183-apmixedsyssyscon4À”ÆZpwrap@1000d000mediatek,mt8183-pwrap4ÐCpwrap ‰¹ñ)+ øspiwrappmicmediatek,mt6358øç U,¶mt6358codecmediatek,mt6358-soundi|4mt6358regulatormediatek,mt6358-regulatorˆ5™5ª5»5Í5à5ñ555(5<�5L5\6l7|8Œ8œ8buck_vdram1¬vdram1»¡ ÓÚLë0Ô0Æ7buck_vcore¬vcore»¡ Ó½¶ëjÈ0buck_vpa¬vpa»¡ Ó7±ÐëÃPú0buck_vproc11¬vproc11»¡ Ó½¶ëjÈ0Æ&buck_vproc12¬vproc12»¡ Ó½¶ëjÈ0Æbuck_vgpu¬vgpu»¡ Ó » ëjÈ0H-_† Æ.buck_vs2¬vs2»¡ ÓÚLë0ÔÆ8buck_vmodem¬vmodem»¡ Ó½¶ëj„0buck_vs1¬vs1»B@Ó'{lë0ÔÆ6ldo_vdram2¬vdram2» 'ÀÓw@ äldo_vsim1¬vsim1»)2àÓ)2àldo_vibr¬vibr»O€Ó2Z <�ldo_vrf12¬vrf12»O€ÓO€xldo_vio18¬vio18»w@Ów@ ŒÆtldo_vusb¬vusb»-ÆÀÓ/M`Ænldo_vcamio¬vcamio»w@Ów@Eldo_vcamd¬vcamd» » Ów@Eldo_vcn18¬vcn18»w@Ów@ldo_vfe28¬vfe28»*¹€Ó*¹€ldo_vsram_proc11 ¬vsram_proc11»¡ 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‰¢ýñ+øgceÆ}auxadc@11001000.mediatek,mt8183-auxadcmediatek,mt8173-auxadc4ñ+#ømain àokayÆYserial@11002000*mediatek,mt8183-uartmediatek,mt6577-uart4  ‰[ ñ*+ øbaudbusàokayµdefaultÃCserial@11003000*mediatek,mt8183-uartmediatek,mt6577-uart40 ñ*+ øbaudbusàokayµdefaultsleepÃDEU\,ybluetoothµdefaultÃFàokayqcom,qca6174-bt %,xñG§nvm_00440302_i2s.binserial@11004000*mediatek,mt8183-uartmediatek,mt6577-uart4@ ‰] ñ*+ øbaudbus àdisabledi2c@11005000mediatek,mt8183-i2c 4P€ ‰Wñ+W+* ømaindma¡+àokayµdefaultÃHɆ i2c@11007000mediatek,mt8183-i2c 4p€€ ‰Qñ+ +* ømaindma¡+àokayµdefaultÃIÉ€touchscreen@10elan,ekth35004µdefaultÃJ U,› 2,œi2c@11008000mediatek,mt8183-i2c 4€€ ‰Rñ+ +*+G ømaindmaarb¡+àokayµdefaultÃKɆ anx7625@58analogix,anx76254XµdefaultÃL %,- 2,I>MKNXOports+port@04endpointePÆ€port@14endpointeQÆTaux-buspanel edp-paneluR‚SportendpointeTÆQi2c@11009000mediatek,mt8183-i2c 4€€ ‰Sñ+ +*+I ømaindmaarb¡+àokayµdefaultÃUÉ€trackpad@15elan,ekth30004µdefaultÃV U,‹trackpad@2c hid-over-i2c4,Œ µdefaultÃV U,‹spi@1100a000mediatek,mt8183-spi+4  ‰xñ6+øparent-clksel-clkspi-clkàokayµdefaultÃW› ¯,Vtpm@0 google,cr504¸B@µdefaultÃX U,™thermal-sensor@1100b000Êmediatek,mt8183-thermal4° ñ+ +# øthermauxadcà+ ‰LçY÷Z [calibration-dataÆ„svs@1100bc00mediatek,mt8183-svs4¼ ‰ñ+ ømain \[(svs-calibration-datat-calibration-datapwm@1100e000mediatek,mt8183-disp-pwm4à ‰€(]6ñ+5ømainmmàokayµdefaultÃ^ƈpwm@11006000mediatek,mt8183-pwm4`60ñ++++++øtopmainpwm1pwm2pwm3pwm4i2c@1100f000mediatek,mt8183-i2c 4ð€ ‰Tñ+ +* ømaindma¡+àokayµdefaultÃ_Ɇ spi@11010000mediatek,mt8183-spi+4 ‰|ñ6+8øparent-clksel-clkspi-clkàokayµdefaultÃ`›flash@0winbond,w25q64dwjedec,spi-nor4¸}x@i2c@11011000mediatek,mt8183-i2c 4€€ ‰Uñ+9+* ømaindma¡+àokayµdefaultÃaɆ spi@11012000mediatek,mt8183-spi+4  ‰ñ6+;øparent-clksel-clkspi-clkàokayµdefaultÃb›cros-ec@0google,cros-ec-spi4¸-ÆÀ U,—µdefaultÃc‹i2c-tunnelgoogle,cros-ec-i2c-tunnelA+sbs-battery@bsbs,sbs-battery4 Sgextcon0google,extcon-usbc-cros-ec|typecgoogle,cros-ec-typec+connector@0usb-c-connector4dualšhost¤sinkkeyboard-controllergoogle,cros-ec-keyb³à ÖDð;<=>?@A B CD}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ipwmgoogle,cros-ec-pwm6 àdisabledspi@11013000mediatek,mt8183-spi+40 ‰‚ñ6+<�øparent-clksel-clkspi-clk àdisabledµdefaultÃd›i2c@11014000mediatek,mt8183-i2c 4@€€ ‰ƒñ+H+*+G ømaindmaarb¡+ àdisabledi2c@11015000mediatek,mt8183-i2c 4P€ ‰„ñ+J+*+I ømaindmaarb¡+ àdisabledi2c@11016000mediatek,mt8183-i2c 4`€ ‰Vñ+D+*+E ømaindmaarb¡+àokayµdefaultÃeɆ da7219@1aµdefaultÃf dlg,da72194 U,¥ý ( diff g +h 9gàokayÆŽda7219_aad F W c2 oô  32_64 ¢ ³  à Ó! ã>i2c@11017000mediatek,mt8183-i2c 4p€€ ‰…ñ+F+*+E ømaindmaarb¡+ àdisabledspi@11018000mediatek,mt8183-spi+4€ ‰†ñ6+Køparent-clksel-clkspi-clk àdisabledµdefaultÃi›spi@11019000mediatek,mt8183-spi+4 ‰‡ñ6+Løparent-clksel-clkspi-clk àdisabledµdefaultÃj›i2c@1101a000mediatek,mt8183-i2c 4 €€ ‰Xñ+b+* ømaindma¡+ àdisabledi2c@1101b000mediatek,mt8183-i2c 4°€ ‰Yñ+c+* ømaindma¡+ àdisabledusb@11201000#mediatek,mt8183-mtu3mediatek,mtu3 4 . > Cmacippc ‰H õklñ+=+Zøsys_ckref_ck úm e+Ùàokay host‹ nusb@11200000'mediatek,mt8183-xhcimediatek,mtk-xhci4 Cmac ‰Iñ+=+Zøsys_ckref_ckàokay+ nhub@1 usb5e3,6104audio-controller@11220000 mediatek,mt8183-audiosyssyscon4"”Æpmt8183-afe-pcmmediatek,mt8183-audio ‰¡ào 'audiosys(]Dñppppp ppppp p p p pp+/+7  0HLKOtuvwxyz{|}~*wøaud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adc_adda6_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_i2s1_bclk_swaud_i2s2_bclk_swaud_i2s3_bclk_swaud_i2s4_bclk_swaud_tdm_clkaud_tml_clkaud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_aud_intbustop_syspll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_clk26m_clkÆŠmmc@11230000mediatek,mt8183-mmc 4#õ ‰Mñ++øsourcehclksource_cgàokayµdefaultstate_uhsÃqr 3¼ ë = O ^ m ~ † Œ( ›s §t ´ ÄU Ûmmc@11240000mediatek,mt8183-mmc 4$á ‰Nñ ++(øsourcehclksource_cgàokayµdefaultstate_uhsÃuv ›w §x éy 3¼ ë ô   ‹ 6 Û C † ´  ÄV+qca-wifi@1 qcom,ath10k4 JGO_FENNEL14dsi-phy@11e50000mediatek,mt8183-mipi-tx4åñZ” j ¶mipi_tx0_pll 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compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typei2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11ovl0ovl-2l0ovl-2l1rdma0rdma1serial0mmc0mmc1opp-sharedphandleopp-hzopp-microvoltrequired-oppsclocksclock-namesoperating-points-v2proc-supplycpudevice_typeregenable-methodcapacity-dmips-mhzcpu-idle-statesdynamic-power-coefficienti-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterrupts#clock-cellsclock-divclock-multclock-output-namesclock-frequencyrangesstatus#interrupt-cellsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxdrive-strengthinput-enablebias-pull-downoutput-lowbias-pull-upmediatek,pull-up-advbias-disablemediatek,pull-down-advoutput-high#power-domain-cellsmediatek,infracfgdomain-supplymediatek,smiinterrupts-extendedmediatek,dmic-modeAvdd-supplyvsys-ldo1-supplyvsys-ldo2-supplyvsys-ldo3-supplyvsys-vcore-supplyvsys-vdram1-supplyvsys-vgpu-supplyvsys-vmodem-supplyvsys-vpa-supplyvsys-vproc11-supplyvsys-vproc12-supplyvsys-vs1-supplyvsys-vs2-supplyvs1-ldo1-supplyvs2-ldo1-supplyvs2-ldo2-supplyvs2-ldo3-supplyvs2-ldo4-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-always-onregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadlinux,keycodeswakeup-sourcememory-regionfirmware-namepinctrl-namespinctrl-0mediatek,rpmsg-namemediatek,larbs#iommu-cells#mbox-cells#io-channel-cellspinctrl-1enable-gpiosreset-gpiosvdd10-supplyvdd18-supplyvdd33-supplyremote-endpointpower-supplybacklighthid-descr-addrmediatek,pad-selectcs-gpiosspi-max-frequency#thermal-sensor-cellsresetsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namespower-domains#pwm-cellsgoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countgoogle,usb-port-idpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapdlg,micbias-lvldlg,mic-amp-in-selVDD-supplyVDDMIC-supplyVDDIO-supplydlg,adc-1bit-rptdlg,btn-avgdlg,btn-cfgdlg,mic-det-thrdlg,jack-ins-debdlg,jack-det-ratedlg,jack-rem-debdlg,a-d-btn-thrdlg,d-b-btn-thrdlg,b-c-btn-thrdlg,c-mic-btn-thrphysmediatek,syscon-wakeupdr_modevusb33-supplyreset-namesbus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-parentsnon-removablemmc-pwrseqcap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104keep-power-in-suspendcap-sdio-irqno-mmcqcom,ath10k-calibration-variant#phy-cellsmediatek,discthinterrupt-namespower-domain-namesmali-supplymboxesmediatek,gce-client-regmediatek,gce-eventsiommus#dma-cellsmediatek,rdma-fifo-sizephy-namesmediatek,scpmediatek,vdecsyspolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionstdout-pathpwmsbrightness-levelsnum-interpolated-stepsdefault-brightness-levelgpioenable-active-highregulator-boot-onno-mapmediatek,platformpinctrl-2mediatek,headset-codeclabellinux,codeio-channelsio-channel-namestemperature-lookup-tabledebounce-intervalsdb-gpios