Ð
þíâ´8Ôì(
ÈÔ´ ,powkiddy,rk2023rockchip,rk35667handsetDPowkiddy RK2023aliasesJ/pinctrl/gpio@fdd60000P/pinctrl/gpio@fe740000V/pinctrl/gpio@fe750000\/pinctrl/gpio@fe760000b/pinctrl/gpio@fe770000h/i2c@fdd40000m/i2c@fe5a0000r/i2c@fe5b0000w/i2c@fe5c0000|/i2c@fe5d0000/i2c@fe5e0000†/serial@fdd50000Ž/serial@fe650000–/serial@fe660000ž/serial@fe670000¦/serial@fe680000®/serial@fe690000¶/serial@fe6a0000¾/serial@fe6b0000Æ/serial@fe6c0000Î/serial@fe6d0000Ö/spi@fe610000Û/spi@fe620000à/spi@fe630000å/spi@fe640000ê/mmc@fe2b0000ï/mmc@fe2c0000ô/mmc@fe000000cpus cpu@0ùcpu,arm,cortex-a55 psci-A€N@`€m€z@Œ€™ªµ
cpu@100ùcpu,arm,cortex-a55psci-A€N@`€m€z@Œ€™ªµcpu@200ùcpu,arm,cortex-a55psci-A€N@`€m€z@Œ€™ªµcpu@300ùcpu,arm,cortex-a55psci-A€N@`€m€z@Œ€™ªµ
l3-cache,cache½ÉCP@bµopp-table-0,operating-points-v2×µopp-408000000âQ–é
»
» Œ0÷œ@opp-600000000â#ÃFé
»
» Œ0opp-816000000â0£,é
»
» Œ0opp-1104000000âAÍ´é
»
» Œ0opp-1416000000âTfré
»
» Œ0opp-1608000000â_Ø"éà˜à˜Œ0opp-1800000000âkIÒéŒ0display-subsystem,rockchip,display-subsystemfirmwarescmi
,arm,scmi-smc‚% protocol@14+µopp-table-1,operating-points-v2µDopp-200000000âëÂé–¨opp-300000000âá£é–¨opp-400000000âׄ閨opp-600000000â#ÃFé–¨opp-700000000â)¹'é
» opp-800000000â/¯éB@hdmi-sound,simple-audio-card8HDMIOi2sh‚okaysimple-audio-card,codec‰simple-audio-card,cpu‰ pmu,arm,cortex-a55-pmu0“äåæçž
psci
,arm,psci-1.0&smctimer,arm,armv8-timer0“
±xin24m,fixed-clockÈn6Øxin24m+µxin32k,fixed-clockÈ€Øxin32këõdefault+sram@10f000
,mmio-sramð ðsram@0,arm,scmi-shmemµsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@ ›œ
satapmaliverxoob“_ sata-phy%7 ‚disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢
satapmaliverxoob“` sata-phy%7 ‚disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@“© ¦§¥
ref_clksuspend_clkbus_clkEperipheral
Mutmi_wide7V”]‚okay usb2-phyv}high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@“ª ©ª¨
ref_clksuspend_clkbus_clkEhostusb2-phyusb3-phy
Mutmi_wide7V•]‚okayinterrupt-controller@fd400000,arm,gic-v3 ý@ýF“ ‹ ±ýA»(Ƶusb@fd800000
,generic-ehciý€“‚ ½¾¼usb ‚disabledusb@fd840000
,generic-ohciý„“ƒ ½¾¼usb ‚disabledusb@fd880000
,generic-ehciýˆ“… ¿À¼usb‚okayusb@fd8c0000
,generic-ohciýŒ“† ¿À¼usb‚okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýµaio-domains&,rockchip,rk3568-pmu-io-voltage-domain‚okayÕãñÿ
)7syscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsysconµ«syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƵsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȵ¬syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɵsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€µ®syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€µ¯clock-controller@fdd00000,rockchip,rk3568-pmucruýÐ+Eµclock-controller@fdd20000,rockchip,rk3568-cruýÒ
xin24m+E Rb€G†ŒëÂÝÐwŽµi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ“. -
i2cpclkë õdefault ‚okaypmic@20,rockchip,rk817 !“Ørk808-clkout1rk808-clkout2
mclk HRHw–+›õdefaultë"#¬º$Æ$Ò$Þ$ê$ö$$$%µÅregulatorsDCDC_REG1&:L¡ d™p|q‘
¨vdd_logicregulator-state-mem·Ð
» DCDC_REG2&:L¡ d™p|q‘¨vdd_gpuµEregulator-state-mem·DCDC_REG3&:‘¨vcc_ddrregulator-state-memìDCDC_REG4&:L2Z d2Z ‘¨vcc_3v3µregulator-state-memìÐ2Z LDO_REG1&:Lw@dw@¨vcca1v8_pmuµMregulator-state-memìÐw@LDO_REG2&:L
» d
» ¨vdda_0v9regulator-state-mem·LDO_REG3&:L
» d
» ¨vdda0v9_pmuregulator-state-memìÐ
» LDO_REG4&:L2Z d2Z
¨vccio_acodecµregulator-state-mem·LDO_REG5&:Lw@d2Z ¨vccio_sdµregulator-state-mem·LDO_REG6&:L2Z d2Z ¨vcc3v3_pmuµregulator-state-memìÐ2Z LDO_REG7&:Lw@dw@¨vcc_1v8µregulator-state-mem·LDO_REG8&:Lw@d2Z ¨vcc1v8_dvpµregulator-state-mem·LDO_REG9&:L*¹€d*¹€¨vcc2v8_dvpregulator-state-mem·BOOST&:LG·`dReÀ¨boostµ%regulator-state-mem·OTG_SWITCH¨otg_switchregulator-state-mem·charger&'9“à_† regulator@1c,tcs,tcs4525†&:L
ß4d5°¨vdd_cpu|ü£$µregulator-state-mem·serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ“t ,
baudclkapb_pclk®''ë(õdefault³À ‚disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×
0
pwmpclkë)õdefaultÊ ‚disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×
0
pwmpclkë*õdefaultÊ ‚disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×
0
pwmpclkë+õdefaultÊ ‚disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0
0
pwmpclkë,õdefaultÊ ‚disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerÕ µpower-domain@7 é-Õpower-domain@8 ÌÍé./0Õpower-domain@9 ÚÛÜé123Õpower-domain@10
ñòé456789Õpower-domain@11 íé:Õpower-domain@13
é;Õpower-domain@14 é<�=>Õpower-domain@15 é?@ABCÕgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$“()'ðjobmmugpu
gpubus-D7‚okayEµœvideo-codec@fdea0400,rockchip,rk3568-vpuýê“‹ðvdpu îï
aclkhclkF7iommu@fdea0800,rockchip,rk3568-iommuýê@“Š
aclkiface îï7µFrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaý뀓Z óôõ
aclkhclksclkV&$%
coreaxiahb7
video-codec@fdee0000,rockchip,rk3568-vepuýî“@ ýþ
aclkhclkG7
iommu@fdee0800,rockchip,rk3568-iommuýî@“? ýþ
aclkiface7
µGmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@“d ÁÂŽ
biuciuciu-driveciu-sample,7ðÑ€Vë reset‚okayEO`mƒHŽëIJKõdefaultœL¨Methernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ“ ðmacirqeth_wake_irq@ †‰‰ÇÃĉÈW
stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refVì
stmmacethŽµNÅÖOéPü ‚disabledmdio,snps,dwmac-mdio stmmac-axi-configµNrx-queues-config/µOqueue0tx-queues-configEµPqueue0vop@fe040000 þ0þ@[vopgamma-lut“”( ÝÞßàá%
aclkhclkdclk_vp0dclk_vp1dclk_vp2Q7 Ž‚okay,rockchip,rk3566-vopRßàwports µport@0 endpoint@2eRµ_port@1 endpoint@4eSµUport@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ?“” ÝÞ
aclkiface7 ‚okayµQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ“D
pclk èdphyT7 apbVŽ‚okay ports port@0endpointeUµSport@1endpointeVµ[panel@0(,powkiddy,rk2023-panelnewvision,nv3051duWõdefaultëXY‹Zportendpointe[µVdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ“E
pclk édphy\7 apbVŽ ‚disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ
“-( æç“(Ú
iahbisfrcecrefõdefaultë]7 ³Ž›‚okay–^µports port@0endpointe_µRport@1endpointe`µÂqos@fe128000,rockchip,rk3568-qossysconþ€ µ-qos@fe138080,rockchip,rk3568-qossysconþ€€ µ<�qos@fe138100,rockchip,rk3568-qossysconþ µ=qos@fe138180,rockchip,rk3568-qossysconþ€ µ>qos@fe148000,rockchip,rk3568-qossysconþ€ µ.qos@fe148080,rockchip,rk3568-qossysconþ€€ µ/qos@fe148100,rockchip,rk3568-qossysconþ µ0qos@fe150000,rockchip,rk3568-qossysconþ µ:qos@fe158000,rockchip,rk3568-qossysconþ€ µ4qos@fe158100,rockchip,rk3568-qossysconþ µ5qos@fe158180,rockchip,rk3568-qossysconþ€ µ6qos@fe158200,rockchip,rk3568-qossysconþ‚ µ7qos@fe158280,rockchip,rk3568-qossysconþ‚€ µ8qos@fe158300,rockchip,rk3568-qossysconþƒ µ9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ µ?qos@fe190280,rockchip,rk3568-qossysconþ€ µ@qos@fe190300,rockchip,rk3568-qossysconþ µAqos@fe190380,rockchip,rk3568-qossysconþ€ µBqos@fe190400,rockchip,rk3568-qossysconþ µCqos@fe198000,rockchip,rk3568-qossysconþ€ µ;qos@fe1a8000,rockchip,rk3568-qossysconþ€ µ1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ µ2qos@fe1a8100,rockchip,rk3568-qossysconþ µ3dfi@fe230000,rockchip,rk3568-dfiþ#“¢apcie@fe260000,rockchip,rk3568-pcie0À@þ&ô[dbiapbconfig<�“KJIHGðsyspmcmsglegacyerr¯( ‚ƒ„…$
aclk_mstaclk_slvaclk_dbipclkauxùpci ¹`ÌbbbbÚëú pcie-phy7Tôôô ô à@@V¡ pipe ‚disabledlegacy-interrupt-controller ‹“Hµbmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@“b °±Š‹
biuciuciu-driveciu-sample,7ðÑ€VÔ reset‚okayEO *! 3ëcdefõdefault >œ¨mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@“c ²³Œ
biuciuciu-driveciu-sample,7ðÑ€VÖ reset‚okayEO *g
3ëhijkõdefault >œ¨spi@fe300000
,rockchip,sfcþ0@“e xv
clk_sfchclk_sfcëlõdefault ‚disabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1“R{}bëÂn6( |zy{}
corebusaxiblocktimer ‚disabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@“4R=AbFÏqFÏq ?C9
mclk_txmclk_rxhclk®m LtxVPQ
tx-mrx-mŽ›‚okayµ i2s@fe410000,rockchip,rk3568-i2s-tdmþA“5REIbFÏqFÏq GK:
mclk_txmclk_rxhclk®mm LrxtxVRS
tx-mrx-mŽõdefaultënopq›‚okay VµÇi2s@fe420000,rockchip,rk3568-i2s-tdmþB“6RMbFÏq OO;
mclk_txmclk_rxhclk®mm LtxrxVT tx-mŽõdefaultërstu› ‚disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC“7 SW<�
mclk_txmclk_rxhclk®mm LtxrxVUV
tx-mrx-mŽ› ‚disabledpdm@fe440000,rockchip,rk3568-pdmþD“L ZY
pdm_clkpdm_hclk®m Lrxëvwxyz{õdefaultVX pdm-m› ‚disabledspdif@fe460000,rockchip,rk3568-spdifþF“f
mclkhclk _\®m Ltxõdefaultë|› ‚disableddma-controller@fe530000,arm,pl330arm,primecellþS@“
q
apb_pclk ˆµ'dma-controller@fe550000,arm,pl330arm,primecellþU@“ q
apb_pclk ˆµmi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ“/ HG
i2cpclkë}õdefault ‚disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[“0 JI
i2cpclkë~õdefault ‚disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\“1 LK
i2cpclkëõdefault ‚disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ]“2 NM
i2cpclkë€õdefault ‚disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^“3 PO
i2cpclkëõdefault ‚okayµ^watchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ`“•
tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa“g RQ
spiclkapb_pclk®'' Ltxrxõdefault낃„ ‚disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb“h TS
spiclkapb_pclk®'' Ltxrxõdefaultë…†‡ ‚disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc“i VU
spiclkapb_pclk®'' Ltxrxõdefault눉Š ‚disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd“j XW
spiclkapb_pclk®'' Ltxrxõdefaultë‹Œ ‚disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe“u
baudclkapb_pclk®''ëŽõdefault³À‚okay “bluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt £Y µY ÂYserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf“v #
baudclkapb_pclk®''ë‘õdefault³À ‚disabledserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg“w '$
baudclkapb_pclk®''ë’õdefault³À ‚disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh“x +(
baudclkapb_pclk®'' ë“õdefault³À ‚disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi“y /,
baudclkapb_pclk®'
'ë”õdefault³À ‚disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj“z 30
baudclkapb_pclk®''
ë•õdefault³À ‚disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk“{ 74
baudclkapb_pclk®''ë–õdefault³À ‚disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl“| ;8
baudclkapb_pclk®''ë—õdefault³À ‚disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm“} ?<�
baudclkapb_pclk®''ë˜õdefault³À ‚disabledthermal-zonescpu-thermal Òd èè ö™tripscpu_alert0
p
Ð?passiveµšcpu_alert1
$ø
Ð?passivecpu_crit
s
Ð ?criticalcooling-mapsmap0
š0
"
ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ
ÿÿÿÿÿÿÿÿgpu-thermal Ò èè ö™tripsgpu-threshold
p
Ð?passivegpu-target
$ø
Ð?passiveµ›gpu-crit
s
Ð ?criticalcooling-mapsmap0
›
"œÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq“sRbf@
®`
tsadcapb_pclkV‚׎
1sõinitdefaultsleepë
Hž
R
\‚okay
r
‰µ™saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr“]
saradcapb_pclkV€ saradc-apb
¤‚okay
¶µ¼pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY
pwmpclkëŸõdefaultÊ‚okayµ¾pwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY
pwmpclkë õdefaultÊ ‚disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY
pwmpclkë¡õdefaultÊ‚okayµÃpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY
pwmpclkë¢õdefaultÊ‚okayµÄpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\
pwmpclkë£õdefaultÊ ‚disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\
pwmpclkë¤õdefaultÊ ‚disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\
pwmpclkë¥õdefaultÊ ‚disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\
pwmpclkë¦õdefaultÊ ‚disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_
pwmpclkë§õdefaultÊ ‚disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_
pwmpclkë¨õdefaultÊ ‚disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_
pwmpclkë©õdefaultÊ ‚disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_
pwmpclkëªõdefaultÊ ‚disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "}
refapbpipeR"bõáVÇ
«
Ô¬
ê‚okayµphy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~
refapbpipeR%bõáVÉ
«
Ô
ê ‚disabledµphy@fe870000,rockchip,rk3568-csi-dphyþ‡ y
pclk
êVº apbŽ ‚disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ…
refpclk z
ê7 apbV»‚okayµTmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ†
refpclk {
ê7 apbV¼ ‚disabledµ\usb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ
phyclkØclk_usbphy0_480m“‡
õ®+‚okayµhost-port
ê ‚disabledotg-port
ê‚okayµusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹
phyclkØclk_usbphy1_480m“ˆ
õ¯+‚okayhost-port
ê‚okayµotg-port
ê ‚disabledµpinctrl,rockchip,rk3568-pinctrlŽ¢a µ°gpio@fdd60000,rockchip,gpio-bankýÖ“! .° !‹ µ!gpio@fe740000,rockchip,gpio-bankþt“" cd° !‹ gpio@fe750000,rockchip,gpio-bankþu“# ef°@ !‹ µggpio@fe760000,rockchip,gpio-bankþv“$ gh°` !‹ µÀgpio@fe770000,rockchip,gpio-bankþw“% ij°€ !‹ µYpcfg-pull-up-µ³pcfg-pull-none:µ±pcfg-pull-none-drv-level-1:Gµµpcfg-pull-none-drv-level-2:Gµ´pcfg-pull-none-drv-level-3:Gµ¸pcfg-pull-up-drv-level-1-Gµ·pcfg-pull-up-drv-level-2-Gµ²pcfg-pull-none-smt:Vµ¶pcfg-output-lowkµ¹acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0v±µcpuebcedpdpemmceth0eth1flashfspifspi-pins`v±±±±±±µlgmac0gmac1gpuhdmitxhdmitxm0-cecv±µ]i2c0i2c0-xfer v ¶
¶µ i2c1i2c1-xfer v¶¶µ}i2c2i2c2m0-xfer v
¶¶µ~i2c3i2c3m0-xfer v¶¶µi2c4i2c4m0-xfer v¶
¶µ€i2c5i2c5m1-xfer v¶¶µi2s1i2s1m0-lrcktxv±µoi2s1m0-mclkv±µ"i2s1m0-sclktxv±µni2s1m0-sdi0v±µpi2s1m0-sdo0v±µqi2s2i2s2m0-lrcktxv±µsi2s2m0-sclktxv±µri2s2m0-sdiv±µti2s2m0-sdov±µui2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clkv±µvpdmm0-clk1v±µwpdmm0-sdi0v±µxpdmm0-sdi1v
±µypdmm0-sdi2v ±µzpdmm0-sdi3v±µ{pmicpmic-int-lv³µ#pmupwm0pwm0m0-pinsv±µ)pwm1pwm1m0-pinsv±µ*pwm2pwm2m0-pinsv±µ+pwm3pwm3-pinsv±µ,pwm4pwm4-pinsv±µŸpwm5pwm5-pinsv±µ pwm6pwm6-pinsv±µ¡pwm7pwm7-pinsv±µ¢pwm8pwm8m0-pinsv ±µ£pwm9pwm9m0-pinsv
±µ¤pwm10pwm10m0-pinsv
±µ¥pwm11pwm11m0-pinsv±µ¦pwm12pwm12m0-pinsv±µ§pwm13pwm13m0-pinsv±µ¨pwm14pwm14m0-pinsv±µ©pwm15pwm15m0-pinsv±µªrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@v²²²²µcsdmmc0-clkv²µdsdmmc0-cmdv²µesdmmc0-detv³µfsdmmc1sdmmc1-bus4@v²²²²µhsdmmc1-clkv²µjsdmmc1-cmdv²µisdmmc1-detv
³µksdmmc2sdmmc2m0-bus4@v²²²²µIsdmmc2m0-clkv²µKsdmmc2m0-cmdv²µJspdifspdifm0-txv±µ|spi0spi0m0-pins0v
±±±µ„spi0m0-cs0v±µ‚spi0m0-cs1v±µƒspi1spi1m0-pins0v
±±±µ‡spi1m0-cs0v±µ…spi1m0-cs1v±µ†spi2spi2m0-pins0v±±±µŠspi2m0-cs0v±µˆspi2m0-cs1v±µ‰spi3spi3m0-pins0v±±
±µspi3m0-cs0v±µ‹spi3m0-cs1v±µŒtsadctsadc-shutorgv±µžtsadc-pinv±µuart0uart0-xfer v³³µ(uart1uart1m1-xfer v³³µŽuart1m1-ctsnv±µuart1m1-rtsnv±µuart2uart2m0-xfer v³³µ‘uart3uart3m0-xfer v³³µ’uart4uart4m0-xfer v³³µ“uart5uart5m0-xfer v³³µ”uart6uart6m0-xfer v³³µ•uart7uart7m0-xfer v³³µ–uart8uart8m0-xfer v³³µ—uart9uart9m0-xfer v³³µ˜vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-btnsbtn-pins-ctrlv³³³³³³ ³
³³³
³³³³³³µ¿btn-pins-vol v³³µÁjoy-muxjoy-mux-env
¹µ»gpio-lcdlcd-rstv±µXsdio-pwrseqwifi-enable-hv±µÆvcc3v3-lcdvcc-lcd-hv±µÈvcc-wifivcc-wifi-hv±µÉadc-joystick
,adc-joystick „ººººë»õdefault<� axis@0ž § °ÿºaxis@1ž § °ÿºaxis@2ž § °ÿºaxis@3ž § °ÿºadc-mux,io-channel-mux‡left_xright_xleft_yright_y
¤„¼ÅparentÖ½ãdµºbacklight,pwm-backlightò$ÿ¾a¨µWbattery,simple-battery0˜&“àC„€h@َɵ?¨àÒ3á@ï¨
?¨àd>p`_=‘¸Z<áðU<¸P;nØK:ÆàF:A9gP<�8§è78À27¦-7_È(7!H#6æ°6˜6+05²5Ø
4u°3á@µ&gpio-keys-control
,gpio-keysë¿õdefaultbutton-a…À
EASTº1button-b…À
SOUTHº0button-down…À
DPAD-DOWNº!button-l1…À
TLº6button-l2…À
TL2º8button-left…À
DPAD-LEFTº"button-r1…À
TRº7button-r2…À
TR2º9button-right…À
DPAD-RIGHTº#button-select…À
SELECTº:button-start…À
STARTº;button-thumbl…À
THUMBLº=button-thumbr…À
THUMBRº>button-up…À
DPAD-UPº button-x…À
NORTHº3button-y…À
WESTº4gpio-keys-vol
,gpio-keys
ëÁõdefaultbutton-vol-down…À
VOLUMEDOWNºrbutton-vol-up…À
VOLUMEUPºsmux-controller ,gpio-mux
*!!
4µ½hdmi-con,hdmi-connector–^?cportendpointeµ`pwm-leds ,pwm-ledsled-0
G
Mstatus
VÿÿÃa¨led-1
G
Mcharging
VÿÿÄa¨sdio-pwrseq,mmc-pwrseq-simple Å
ext_clockëÆõdefault
eÈYµHsound,simple-audio-card
8rk817_extOi2sh
|HeadphoneHeadphones
–HeadphonesHPOLHeadphonesHPORsimple-audio-card,codec‰Åsimple-audio-card,cpu‰Çregulator-vcc3v3-lcd0,regulator-fixed
°!
µëÈõdefault:L2Z d2Z ¨vcc3v3_lcd0_n£µZregulator-state-mem·regulator-vcc-sys,regulator-fixed&:L9ûÀd9ûÀ¨vcc_sysµ$regulator-vcc-wifi,regulator-fixed
µ
°!ëÉõdefault&:L2Z d2Z ¨vcc_wifiµL interrupt-parent#address-cells#size-cellscompatiblechassis-typemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc1mmc2mmc3device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablevmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointbacklightreset-gpiosvdd-supplyddc-i2c-busrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpsd-uhs-sdr104dma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsio-channelspoll-intervalabs-flatabs-fuzzabs-rangelinux,codeio-channel-namesmux-controlssettle-time-uspower-supplypwmscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0labelautorepeatmux-gpios#mux-control-cellscolorfunctionmax-brightnesspost-power-on-delay-mssimple-audio-card,widgetssimple-audio-card,routinggpioenable-active-high