Ð þíÓ8Ç|( žÇD %,embedfire,lubancat-1rockchip,rk35667EmbedFire LubanCat 1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe2b0000ì/mmc@fe310000cpus cpu@0ñcpu,arm,cortex-a55ýpsci%9€F@X€e€r@„€‘¢­ cpu@100ñcpu,arm,cortex-a55ýpsci%9€F@X€e€r@„€‘¢­ cpu@200ñcpu,arm,cortex-a55ýpsci%9€F@X€e€r@„€‘¢­ cpu@300ñcpu,arm,cortex-a55ýpsci%9€F@X€e€r@„€‘¢­ l3-cache,cacheµÁ;H@Z­opp-table-0,operating-points-v2Ï­opp-408000000ÚQ– á »  » Œ0ïœ@opp-600000000Ú#ÃF á »  » Œ0opp-816000000Ú0£, á »  » Œ0opp-1104000000ÚAÍ´ á »  » Œ0opp-1416000000ÚTfr á »  » Œ0opp-1608000000Ú_Ø" áà˜à˜Œ0opp-1800000000ÚkIÒ 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Eutmi_wide/N•Uzokayinterrupt-controller@fd400000 ,arm,gic-v3 ýý@ýF ‹ ƒ˜©ýA³(¾­usb@fd800000 ,generic-ehciýý€ ‹‚½¾¼usbzokayusb@fd840000 ,generic-ohciýý„ ‹ƒ½¾¼usbzokayusb@fd880000 ,generic-ehciýýˆ ‹…¿À¼usbzokayusb@fd8c0000 ,generic-ohciýýŒ ‹†¿À¼usbzokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýý­[io-domains&,rockchip,rk3568-pmu-io-voltage-domainzokayÍÛé÷!syscon@fdc50000ýýÅ ,rockchip,rk3566-pipe-grfsyscon­¬syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýýÆ­syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýýÈ­­syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýýÉ­®syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýýÊ€­¯syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýýÊ€€­°clock-controller@fdd00000,rockchip,rk3568-pmucruýýÐ#/­clock-controller@fdd20000,rockchip,rk3568-cruýýÒxin24m#/<� L€G†Œ ëÂax­i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýýÔ ‹.- i2cpclkã ídefault zokayregulator@1c ,tcs,tcs4525ý…¢vdd_cpu±Å× 5ïŒ0ü!­regulator-state-mem'pmic@20,rockchip,rk809ý "‹Ðrk808-clkout1rk808-clkout2ídefaultã#@a#o${$‡$“$Ÿ$«$·$Ã$Ï$regulatorsDCDC_REG1 ¢vdd_logic±Åס ï™pqÛregulator-state-mem'DCDC_REG2¢vdd_gpu±Åס ï™pqÛ­Cregulator-state-mem'DCDC_REG3¢vcc_ddr±ÅÛregulator-state-memòDCDC_REG4¢vdd_npu±Åס ï™pqÛregulator-state-mem'DCDC_REG5¢vcc_1v8±Å×w@ïw@­regulator-state-mem'LDO_REG1¢vdda0v9_imageÅ±× » ï » ­Wregulator-state-mem'LDO_REG2 ¢vdda_0v9±Å× » ï » regulator-state-mem'LDO_REG3 ¢vdda0v9_pmu±Å× » ï » regulator-state-memò » LDO_REG4 ¢vccio_acodec±Å×2Z ï2Z ­regulator-state-mem'LDO_REG5 ¢vccio_sd±Å×w@ï2Z ­regulator-state-mem'LDO_REG6 ¢vcc3v3_pmu±Å×2Z ï2Z ­regulator-state-memò 2Z LDO_REG7 ¢vcca_1v8±Å×w@ïw@­Ÿregulator-state-mem'LDO_REG8 ¢vcca1v8_pmu±Å×w@ïw@regulator-state-memò w@LDO_REG9¢vcca1v8_image±Å×w@ïw@­Xregulator-state-mem'SWITCH_REG1¢vcc_3v3±Å­regulator-state-mem'SWITCH_REG2 ¢vcc3v3_sd±Å­^regulator-state-mem'serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýýÕ ‹t ,baudclkapb_pclk&%%ã&ídefault+8 zdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý× 0 pwmpclkã'ídefaultB zdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý× 0 pwmpclkã(ídefaultB zdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý×  0 pwmpclkã)ídefaultB zdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý×0 0 pwmpclkã*ídefaultB zdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýýÙpower-controller!,rockchip,rk3568-power-controllerM ­power-domain@7ýa+Mpower-domain@8ýÌÍ a,-.Mpower-domain@9ý ÚÛÜ a/01Mpower-domain@10ý ñòa234567Mpower-domain@11ý ía8Mpower-domain@13ý a9Mpower-domain@14ý a:;<�Mpower-domain@15ýa=>?@AMgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýýæ@$‹()' hjobmmugpugpubus%B/zokayxC­œvideo-codec@fdea0400,rockchip,rk3568-vpuýýê ‹‹hvdpuîï aclkhclk„D/ iommu@fdea0800,rockchip,rk3568-iommuýýê@ ‹Š aclkifaceîï/ ‹­Drga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýýë€ ‹ZóôõaclkhclksclkN&$% ˜coreaxiahb/ video-codec@fdee0000,rockchip,rk3568-vepuýýî ‹@ýþ aclkhclk„E/ iommu@fdee0800,rockchip,rk3568-iommuýýî@ ‹?ýþ aclkiface/ ‹­Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ@ ‹d ÁÂŽbiuciuciu-driveciu-sample¤¯ðÑ€Në˜reset zdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aýþ‹ hmacirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refNì ˜stmmacethx½FÍÞGñHzokay rgmiioutput #I3 I$ø† <�‰†a‡ÅLsY@ídefaultãJKLMN^g pOmdio,snps,dwmac-mdio phy@0,ethernet-phy-ieee802.3-c22ý­Ostmmac-axi-config{…•­Frx-queues-config¥­Gqueue0tx-queues-config»­Hqueue0vop@fe040000 ýþ0þ@Ñvopgamma-lut ‹”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2„P/ xzokay,rockchip,rk3566-vop<�ßàaports ­port@0ý endpoint@2ýÛQ­Yport@1ý port@2ý iommu@fe043e00,rockchip,rk3568-iommu ýþ>þ? ‹”ÝÞ aclkiface‹/ zokay­Pdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiýþ ‹DpclkèdphyR/ ˜apbNx zdisabledports port@0ýport@1ýdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiýþ ‹EpclkédphyS/ ˜apbNx zdisabledports port@0ýport@1ýhdmi@fe0a0000,rockchip,rk3568-dw-hdmiýþ  ‹-(æç“(Úiahbisfrcecrefídefault ãTUV/ +xëzokayüW X­ports port@0ýendpointÛY­Qport@1ýendpointÛZ­ºqos@fe128000,rockchip,rk3568-qossysconýþ€ ­+qos@fe138080,rockchip,rk3568-qossysconýþ€€ ­:qos@fe138100,rockchip,rk3568-qossysconýþ ­;qos@fe138180,rockchip,rk3568-qossysconýþ€ ­<�qos@fe148000,rockchip,rk3568-qossysconýþ€ ­,qos@fe148080,rockchip,rk3568-qossysconýþ€€ ­-qos@fe148100,rockchip,rk3568-qossysconýþ ­.qos@fe150000,rockchip,rk3568-qossysconýþ ­8qos@fe158000,rockchip,rk3568-qossysconýþ€ ­2qos@fe158100,rockchip,rk3568-qossysconýþ ­3qos@fe158180,rockchip,rk3568-qossysconýþ€ ­4qos@fe158200,rockchip,rk3568-qossysconýþ‚ ­5qos@fe158280,rockchip,rk3568-qossysconýþ‚€ ­6qos@fe158300,rockchip,rk3568-qossysconýþƒ ­7qos@fe180000,rockchip,rk3568-qossysconýþ qos@fe190000,rockchip,rk3568-qossysconýþ ­=qos@fe190280,rockchip,rk3568-qossysconýþ€ ­>qos@fe190300,rockchip,rk3568-qossysconýþ ­?qos@fe190380,rockchip,rk3568-qossysconýþ€ ­@qos@fe190400,rockchip,rk3568-qossysconýþ ­Aqos@fe198000,rockchip,rk3568-qossysconýþ€ ­9qos@fe1a8000,rockchip,rk3568-qossysconýþ€ ­/qos@fe1a8080,rockchip,rk3568-qossysconýþ€€ ­0qos@fe1a8100,rockchip,rk3568-qossysconýþ ­1dfi@fe230000,rockchip,rk3568-dfiýþ# ‹ [pcie@fe260000,rockchip,rk3568-pcie0ýÀ@þ&ôÑdbiapbconfig<�‹KJIHGhsyspmcmsglegacyerr)(‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxñpci˜3`F\\\\Tetƒ’š pcie-phy/Tûôôô ô à@@N¡˜pipe zokay ¤"°]legacy-interrupt-controller˜ƒ ‹H­\mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ+@ ‹b °±Š‹biuciuciu-driveciu-sample¤¯ðÑ€NÔ˜resetzokayÀÌÖèù  ^ ídefaultã_`abmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ,@ ‹c ²³Œbiuciuciu-driveciu-sample¤¯ðÑ€NÖ˜reset zdisabledspi@fe300000 ,rockchip,sfcýþ0@ ‹exvclk_sfchclk_sfcãcídefault zdisabledmmc@fe310000,rockchip,rk3568-dwcmshcýþ1 ‹<�{}| L ëÂn6 ëÂ(|zy{}corebusaxiblocktimerzokay̯ ë + :ídefault ãdef Hi2s@fe400000,rockchip,rk3568-i2s-tdmýþ@ ‹4<�=ALFÏqFÏq?C9mclk_txmclk_rxhclk&g VtxNPQ ˜tx-mrx-mxë zdisabled­ i2s@fe410000,rockchip,rk3568-i2s-tdmýþA ‹5<�EILFÏqFÏqGK:mclk_txmclk_rxhclk&gg VrxtxNRS ˜tx-mrx-mxídefault0ãhijklmnopqrsëzokay `i2s@fe420000,rockchip,rk3568-i2s-tdmýþB ‹6<�MLFÏqOO;mclk_txmclk_rxhclk&gg VtxrxNT˜tx-mxídefaultãtuvwë zdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmýþC ‹7SW<�mclk_txmclk_rxhclk&gg VtxrxNUV ˜tx-mrx-mxë zdisabledpdm@fe440000,rockchip,rk3568-pdmýþD ‹LZYpdm_clkpdm_hclk&g  Vrxãxyz{|}ídefaultNX˜pdm-më zdisabledspdif@fe460000,rockchip,rk3568-spdifýþF ‹f mclkhclk_\&g Vtxídefaultã~ë zdisableddma-controller@fe530000,arm,pl330arm,primecellýþS@‹  {  apb_pclk ’­%dma-controller@fe550000,arm,pl330arm,primecellýþU@‹ {  apb_pclk ’­gi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþZ ‹/HG i2cpclkãídefault  zdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ[ ‹0JI i2cpclkã€ídefault  zdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ\ ‹1LK i2cpclkãídefault  zdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ] ‹2NM i2cpclkã‚ídefault  zdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ^ ‹3PO i2cpclkãƒídefault  zdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtýþ` ‹• tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiýþa ‹gRQspiclkapb_pclk&%% Vtxrxídefault ã„…†  zdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiýþb ‹hTSspiclkapb_pclk&%% Vtxrxídefault ㇈‰  zdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiýþc ‹iVUspiclkapb_pclk&%% Vtxrxídefault ㊋Œ  zdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiýþd ‹jXWspiclkapb_pclk&%% Vtxrxídefault ㍎  zdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartýþe ‹ubaudclkapb_pclk&%%ãídefault+8 zdisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartýþf ‹v# baudclkapb_pclk&%%ã‘ídefault+8zokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartýþg ‹w'$baudclkapb_pclk&%%ã’ídefault+8 zdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartýþh ‹x+(baudclkapb_pclk&%% ã“ídefault+8 zdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartýþi ‹y/,baudclkapb_pclk&% % ã”ídefault+8 zdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþj ‹z30baudclkapb_pclk&% % ã•ídefault+8 zdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþk ‹{74baudclkapb_pclk&%%ã–ídefault+8 zdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþl ‹|;8baudclkapb_pclk&%%ã—ídefault+8 zdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþm ‹}?<�baudclkapb_pclk&%%ã˜ídefault+8 zdisabledthermal-zonescpu-thermal d ³è Á™tripscpu_alert0 Ñp ÝÐøpassive­šcpu_alert1 Ñ$ø ÝÐøpassivecpu_crit Ñs ÝÐ øcriticalcooling-mapsmap0 èš0 í ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal  ³è Á™tripsgpu-threshold Ñp ÝÐøpassivegpu-target Ñ$ø ÝÐøpassive­›gpu-crit Ñs ÝÐ øcriticalcooling-mapsmap0 è› íœÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcýþq ‹s<�Lf@ ®`tsadcapb_pclkN‚×x üsíinitdefaultsleep㝠ž  'zokay = T­™saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcýþr ‹]saradcapb_pclkN€ ˜saradc-apb ozokay Ÿpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþnZY pwmpclkã ídefaultB zdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþnZY pwmpclkã¡ídefaultB zdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþn ZY pwmpclkã¢ídefaultB zdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþn0ZY pwmpclkã£ídefaultB zdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo]\ pwmpclkã¤ídefaultB zdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo]\ pwmpclkã¥ídefaultB zdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo ]\ pwmpclkã¦ídefaultB zdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo0]\ pwmpclkã§ídefaultB zdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp`_ pwmpclkã¨ídefaultB zdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp`_ pwmpclkã©ídefaultB zdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp `_ pwmpclkãªídefaultB zdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp0`_ pwmpclkã«ídefaultB zdisabledphy@fe830000,rockchip,rk3568-naneng-combphyýþƒ"} refapbpipe<�"LõáNÇ ¬ Ÿ­ µzokay­phy@fe840000,rockchip,rk3568-naneng-combphyýþ„%~ refapbpipe<�%LõáNÉ ¬ Ÿ® µzokay­phy@fe870000,rockchip,rk3568-csi-dphyýþ‡ypclk µNº˜apbx zdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyýþ… refpclkz µ/ ˜apbN» zdisabled­Rmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyýþ† refpclk{ µ/ ˜apbN¼ zdisabled­Susb2phy@fe8a0000,rockchip,rk3568-usb2phyýþŠphyclkÐclk_usbphy0_480m ‹‡ À¯#zokay­host-port µzokay­otg-port µzokay­usb2phy@fe8b0000,rockchip,rk3568-usb2phyýþ‹phyclkÐclk_usbphy1_480m ‹ˆ À°#zokayhost-port µzokay­otg-port µzokay­pinctrl,rockchip,rk3568-pinctrlx[ û­±gpio@fdd60000,rockchip,gpio-bankýýÖ ‹!.  Ð à±  샘­"gpio@fe740000,rockchip,gpio-bankýþt ‹"cd Ð à±  샘gpio@fe750000,rockchip,gpio-bankýþu ‹#ef Ð à±@  샘­Igpio@fe760000,rockchip,gpio-bankýþv ‹$gh Ð à±`  샘gpio@fe770000,rockchip,gpio-bankýþw ‹%ij Ð à±€  샘pcfg-pull-up ø­´pcfg-pull-none ­²pcfg-pull-none-drv-level-1  ­¶pcfg-pull-none-drv-level-2  ­µpcfg-pull-none-drv-level-3  ­¹pcfg-pull-up-drv-level-1 ø ­¸pcfg-pull-up-drv-level-2 ø ­³pcfg-pull-none-smt  !­·acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 6²­cpuebcedpdpemmcemmc-bus8€ 6 ³ ³³³³³³³­demmc-clk 6³­eemmc-cmd 6³­feth0eth1flashfspifspi-pins` 6²²²²²²­cgmac0gmac1gmac1m1-miim 6²²­Jgmac1m1-rx-bus20 6²² ²­Lgpuhdmitxhdmitxm0-cec 6²­Vhdmitx-scl 6²­Thdmitx-sda 6²­Ui2c0i2c0-xfer 6 · ·­ i2c1i2c1-xfer 6 · ·­i2c2i2c2m0-xfer 6 ··­€i2c3i2c3m0-xfer 6··­i2c4i2c4m0-xfer 6 · ·­‚i2c5i2c5m0-xfer 6 · ·­ƒi2s1i2s1m0-lrckrx 6²­ki2s1m0-lrcktx 6²­ji2s1m0-sclkrx 6²­ii2s1m0-sclktx 6²­hi2s1m0-sdi0 6 ²­li2s1m0-sdi1 6 ²­mi2s1m0-sdi2 6 ²­ni2s1m0-sdi3 6²­oi2s1m0-sdo0 6²­pi2s1m0-sdo1 6²­qi2s1m0-sdo2 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplysupports-sdbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removablesupports-emmcdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabellinux,default-triggerdefault-stateenable-active-highstartup-delay-us